Abstract: A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

Abstract: A replacement latch for a male RJ45 plug is presented. The replacement latch includes a housing and a latch within the housing, wherein the latch includes: a substantially U-shaped component having a middle section that joins a first arm of the U-shaped component to a second arm of the U-shaped component, wherein the first arm terminates at a first arm end that has a shape that is geometrically similar to a standard RJ45 retention protrusion, and wherein the middle section is rotatable about a pivot point that is inside the housing, and a horizontal activator having a depressor that is in sliding contact with the second arm, wherein a horizontal movement, in a first direction, of the horizontal activator causes the middle section to rotate about the pivot point to cause the first arm end to engage against a retention lip in a female RJ45 receptacle.

Abstract: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.

Abstract: System, method and program product for tracing first, second and third processes for producing a product. First, second and third process instances for the first, second and third processes, respectively, are generated. Tracing information is stored in association with the first, second and third process instances to indicate respective execution conditions. The third process instance is executed after the second process instance, and the second process instance is executed after the first process instance. The first process instance yields a product which is subject to the second process instance, and the second process instance yields a product which is subject to the third process instance. A first pointer indicates that the second process instance follows the first process instance, and a second pointer indicates that the third process instance follows the second process instance.

Abstract: An apparatus, system and method for synchronizing an asynchronous mirror volume using a synchronous mirror volume by tracking change information when data is written to a primary volume and not yet written to an asynchronous mirror, and storing the change information on both the primary storage system and the synchronous mirror system. In the event the primary storage system becomes unavailable, the asynchronous mirror is synchronized by copying data identified by the change information stored in the synchronous mirror system and using the synchronous mirror as the copy data source.

Abstract: A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.

Abstract: A system and method for protecting data transmitted across a private network is disclosed. A secure channel is established so that the client computer can securely transmit a password to the server computer. Once the password has been transmitted, future transmissions use the password to encrypt data by the sending computer and decipher the data at the receiving computer. In one embodiment, passwords expire after a certain amount of time and are thereafter renegotiated. In another embodiment, the password is successively modified by a counter value further preventing unauthorized persons from discovering the password used to encrypt the data. By using passwords rather than public-key encryption methods, less system resources are required to maintain data confidentiality. An information handling system securely transmitting data within a private network as well as a computer program product programmed to perform the encryption processing are further disclosed.

Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Abstract: A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

Abstract: A performance monitor includes at least one Monitor Mode Control Register (MMCR) and plural Performance Control Monitors (PMCs). Each PMC is controlled by the MMCR to pair or group the PMCs so that the overflow from one PMC can be directed to its pair/group. By coupling the PMCs so that overflow from one can be directed to another, the effective size of the counters can be increased.

Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.

Abstract: A method and article of manufacture, implementing the method, allocates space for a dataset. The dataset has an initial area and zero or more additional allocated areas to provide space for storing the dataset. The size of a new additional area is determined. The new additional area is associated with a new area number, and the size of the new additional area is based on the new area number. Additional space for the dataset is allocated based on the size of the new additional area.

Abstract: A method, system and apparatus for service management. A service management system can include a name resolution adapter disposed in a PSTN. The name resolution adapter can be communicatively linked to a LIDB also disposed within the PSTN. Notably, an enterprise application can be configured to manage service subscriptions and can enjoy communicative couplings both to the name resolution adapter over a data communications network and also to a switch disposed in the PSTN. Finally, service renewal logic can be associated with the enterprise application and programmed to renew service subscriptions for calling ones of subscribers to the service subscriptions based upon identifying data for the calling ones of the subscribers as received in the enterprise application over the data communications network from the name resolution adapter.

Abstract: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

Abstract: A computer implemented system and method for evaluating the impact of a project implementation within a customer situation allows building a business case model for each category of products to be associated within the project implementation and then consolidating all the category business case models into a final general business case model.

Abstract: The aspects of the present invention provide for an apparatus for conveying air into foam so that the flow of air within the foam may be monitored to determine one or more characteristics of the foam. The apparatus includes a nozzle and a member having a substantially planar surface. The nozzle includes a tube sized and dimensioned to be inserted easily into the foam. The tube has a wall and an aperture formed in the wall. The aperture is sized and dimensioned to allow air to flow through the aperture and into the foam, and the aperture extends partially about the circumference of the tube. The member is mounted to the nozzle and is also connected to an air flow meter.

Abstract: An apparatus for providing uniform axial load distribution for laminate layers of multilayer ceramic chip carriers includes a base plate configured to support a plurality of green sheet layers thereon, the base plate having at least one resiliently mounted load support bar disposed adjacent outer edges of the base plate. The load support bar is mounted on one or more biasing members such that the top surface of the support bar extends above the top surface of the base plate by a selected distance.

Abstract: The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.

Abstract: A computerized method (300) and software product (200) is provided for querying and modifying a Multi-Level Data Structure (106) stored in a Text-to-Speech (100) engine of a data processing system having a Central Processing Unit (202), a processing system memory (203), and an operating system (201), using an application program written in an interpretive programming language. The method includes the steps of initializing (302) by means of the CPU implementing a set of commands, a data processing environment for processing the application program, processing (306) the application program, where the processing includes identifying a marked command that encapsulates a DPMS program, and upon identifying a marked command, operating (318) on the MLDS using a DPMS interpreter for producing a result from the MLDS, the result available to the application program during execution of the application program.