Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: A method for implementing large scale parallel file I/O processing includes steps of: separating processing nodes into compute nodes specializing in computation and I/O nodes (computer processors restricted to running I/O daemons); organizing the compute nodes and the I/O nodes into processing sets, the processing sets including: one dedicated I/O node corresponding to a plurality of compute nodes. I/O related system calls are received in the compute nodes then sent to the corresponding I/O nodes. The I/O related system calls are processed through a system I/O daemon residing in the I/O node. The plurality of compute nodes are evenly distributed across participating processing sets. Additionally, for collective I/O operations, compute nodes from each processing set are assigned as I/O aggregators to issue I/O requests to their corresponding I/O node, wherein the I/O aggregators are evenly distributed across the processing set.

Abstract: A method for updating the return on investment (ROI) templates used by business consultants. The present invention comprises a Template Evaluation Program (TEP) and a Template Analysis Program (TAP). The TEP compares the default template to the templates modified by the consultants for the customer's ROI analysis and assigns an effectiveness factor to the modified templates. The TAP develops a data list from the default templates and the effectiveness factors and plots the data on a histogram. The TAP performs a statistical analysis for each parameter and updates the default template parameter values if the data fits a normal distribution curve. If the data forms more than one peak on the histogram, then the TAP uses one peak to update the default template and uses the second peak to create a new template. The new template's parameter value is derived from the data in the second peak.

Abstract: Handling a magnetic tape cartridge comprises the steps of reading cartridge mount information from the cartridge memory; determining from the cartridge mount information whether the present mount is the first mount of the magnetic tape cartridge; and if so, fast forward and rewind the magnetic tape of the magnetic tape cartridge, e.g., the fast forward is to end of tape (EOT) and the rewind is to beginning of tape (BOT). Alternatively, if the cartridge mount information indicates the present mount is the first mount of the magnetic tape cartridge; monitoring input/output with respect to the magnetic tape cartridge for write errors during the mount; determining whether the number of monitored write errors meets a predetermined threshold; and if so, fast forward and rewind the magnetic tape of the magnetic tape cartridge.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment replace an element in a query with a backup if the element is not available, but the backup is available. An element may also be removed from the query if the element is not required. In various embodiments, the element may be a table or a user-defined function. In this way, the query may still execute even if the element is not available.

Abstract: A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.

Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.

Abstract: An application for middleware sign-on is provided. A secure engine in the middleware generates a soft keyboard and scroll area. The scroll area includes coordinates associated with the soft keyboard. A selector is generated overlaid on the soft keyboard. The selector moves with respect to the soft keyboard in response to cursor movement within the scroll area. As the cursor movement causes the selector, the secure engine generates and stores false data key selections. When a user selects a data key with the selector, the middleware generates and stores the valid data key entry. The middleware stores both the valid data key selections and the false data key selections in the same area. Once the user submits his completed selection, or data, the middleware processes the data.

Abstract: A virtual workspace is provided for a user with a number of electronic devices, in which information can be exchanged among the electronic devices through a number of connections between the electronic devices. The virtual workspace is provided by determining where services are located and the type of the services, determining one or more data formats associated with data accessible by one or more of the electronic devices. A portion of the data has a given one of one or more data formats. An electronic device is selected based at least in part on predetermined criteria and the given data format. A route through the connections to the selected electronic device is determined, where the route may comprise a given one or more of the connections. At least the portion of the data associated with the given data format is routed to the selected electronic device. The portion of the data is utilizable for presentation by the selected electronic device when received by the selected electronic device.

Abstract: Provides a diagnostic apparatus for diagnosing a measured object based on time-series data of a plurality of parameters measured from the measured object. An example of an apparatus includes a change-point score calculating portion for calculating a time-series change-point score with which each of the plurality of parameters changes according to passage of time based on the time-series data on the parameter, a change-point correlation calculating portion for calculating a change-point correlation indicating strength by which each of the plurality of parameters is associated with each of other parameters based on the change-point scores of the parameter and the other parameter, and a parameter outputting portion for outputting a set of parameters of which calculated degrees of associations are higher than a predetermined reference change-point correlation as a set of mutually strongly associated parameters.

Abstract: A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided.

Abstract: First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A system, method, and computer program product for managing a retention period for electronic content data are disclosed. The method includes running a records manager system. The records manager system defines a retention period for a plurality of electronic content data. The records manager system instructs a digital rights manager system to protect each of the plurality of electronic content data. Each of the plurality of electronic content data are protected with at least one usage policy for at least one of the plurality of electronic content data related to the retention period as governed by the records manager system. The defined retention period is logged, for later auditing, for each of the plurality of the electronic content data.

Abstract: A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node.

Abstract: In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the kernel. The application designs an optimum cache footprint for a data set from said application. The objects, advantages and features of the present invention will become apparent from the following detailed description. In one embodiment of the present invention, the application transmits a memory reallocation order to a memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to the memory manager further comprises the application transmitting a memory reallocation order containing the optimum cache footprint to the memory manager.

Abstract: A method and system for synchronizing M application rules across N database instances. N and M are each at least 2. A rule synchronization agent is executed which updates N1 database instances with the M application rules and does not update a remaining N-N1 database instances with the M application rules if N1 is equal to N. N1 is at least 1. If N1 is less than N, then each of the remaining N-N1 database instances include a first and/or second characteristic. The first characteristic is that the remaining database instances include the M application rules upon initiation of the executing. The second characteristic is that the agent is unable to access the remaining database instance during the executing.

Abstract: A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

Abstract: A computer implemented method, data processing system, and processor are provided for implementation of thermal throttling logic. A sensed temperature value is received from a digital thermal sensor representing a current temperature of a unit associated with the digital thermal sensor in the integrated circuit. The sensed temperature is reported as the current temperature in a status register. The unit in the integrated circuit is throttled in response to the current temperature exceeding a first predetermined value.

Abstract: A system and method of remotely loading artifacts is disclosed. The method involves storing and indexing a plurality of artifacts in a centralized location. A query is received from a client to locate an artifact, and the artifact is located within the central location. A reply is then returned to the client, wherein the reply includes a location of the artifact. In one embodiment, the method of remotely loading artifacts further involves the artifacts being previously extracted from an application during the installation of the application.

Abstract: An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.