Abstract: An ergonomic computer mouse has support surfaces that are adjustable in two directions. The mouse includes a pivot mechanism that couples an upper and lower portion of the mouse housing together. The pivot mechanism may allow a user to adjust the upper and lower housing portions in pitch and roll directions with respect to one another.

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: To provide a peripheral device and a computer system, each being arranged to allow both of external and internal attachments of the peripheral device to the computer system such that, in case of the external attachment, the peripheral device can be attached to the computer system in a manner compatible with the conventional attachment method and yet it does not require any dedicated attachment device as before. A computer system 100 comprises a container 140 for containing a peripheral device 130 as an internal device, a cable 410 for attaching the peripheral device 130 to the system 100 as an external device, and a connector 434 for connecting the cable 410. Also, the peripheral device 130 has a connector 132 for internal attachment and a connector 310 for external attachment. When the peripheral device 130 is contained in the container 140, it is electrically connected to the system 100 and operates as a part thereof.

Abstract: WFMS execute a multitude of process models consisting of a network of potentially distributed activities. Within this structure is the implementation of events within WFMS like any other process activity. Thus events are implemented as event-activities, a special type of an activity within said WFMS. Such an event-activity can manage an event occurring internal or external to the WFMS.

Abstract: A method, apparatus, and article of manufacture for a computer implemented storage mechanism for persistent objects in a database management system. A statement is executed in a computer. The statement is performed by the computer to manipulate data in a database stored on a data storage device connected to the computer. It is determined that an object is to be stored in an inline buffer. When the object can be entirely stored in the inline buffer, the object is stored in the inline buffer. When the object cannot be entirely stored in the inline buffer, a selected portion of the object is stored in the inline buffer and the remaining portion of the object is stored as a large object.

Abstract: A system and method for translating source code, comprising high level source code with embedded SQL statements, to p-code or machine-language instructions by a one-pass parsing mechanism. The one-pass parsing mechanism generates executable code without the need to generate an intermediate file. Additionally, the p-code or machine-language instructions are annotated with references to the line numbers of the corresponding source code, thereby allowing a source level debugger to debug the source code with embedded SQL statements.

Abstract: A method and system for allocating and freeing storage are provided. The method can be built on top of any existing storage management algorithm. The method is described as being built upon the heap storage algorithm most often associated with the C programming environment. The method operates by breaking all storage requests into a fixed number of pools. Each pool is then managed by three tiers of management. The first tier is a so-called quick pool consisting of storage blocks which have already been used and freed and are managed on a LIFO queue. The second tier is made up of cell pool extents that are carved from the heap and then further subdivided into blocks of the appropriate size for each pool. The third tier is made up of the existing heap management algorithms or any other storage management algorithm. The method relies on atomic hardware instructions for removing blocks from the quick pools and cell extents.

Abstract: A method, apparatus, and article for solving the year 2000 problem involves limited modifications in the data definition portions of the source code and compiler or interpreter support for processing the modified source code. Fields in the source code that contain a year or date values are identified and, for each such field, the user selects an appropriate technique (for example, expansion, compression or windowing). The user modifies the data definition for each identified field, by adding new attributes to request the selected technique. The user then compiles or interprets the program and resolves any ambiguous references to the variables whose definitions were modified. This procedure is applied, module by module, and each processed module is merged into production, after testing, by using a compiler option to disable the use of the new attributes.

Abstract: A method is described for operating a data processing system having a plurality of processors to sort a set of data records each having an associated key for governing the sort process. The method comprises determining a range for the key values by sampling the key values. The range is divided into a plurality of quantiles, one for each processor, each quantile having a respective index. At each processor, a plurality of buckets are defined, each bucket corresponding to a respective one of a plurality M.sub.p of subintervals in the quantile, each subinterval having a respective index. The index of the quantile in which the key value lies and the index of the subinterval in which the key value lies are determined directly from the key values using fast operations. Each key is distributed to the processor corresponding to the quantile in which the key value lies.

Abstract: The processor includes at least a lower and a higher level non-inclusive cache, and a system bus controller. The system bus controller snoops commands on the system bus, and supplies the snooped commands to each level of cache. Additionally, the system bus controller receives the response to the snooped command from each level of cache, and generates a combined response thereto. When generating responses to the snooped command, each lower level cache supplies its responses to the next higher level cache. Higher level caches generate their responses to the snooped command based in part upon the response of the lower level caches. Also, high level caches determine whether or not the cache address, to which the real address of the snooped command maps, matches the cache address of at least one previous high level cache query.

Abstract: An apparatus for polarization conversion having a light source for supplying vertically and horizontally linearly polarized light to an optical path and a parabolic mirror disposed in the optical path and proximate to the light source. In different embodiments, the parabolic mirror has a mirror coating to induce a phase shift of 0.degree., 90.degree., or an arbitrary phase shift between incident light and reflected light. A polarizer, preferably a reflective polarizer film, is disposed in the optical path for reflecting light of one of the linear polarizations and for transmitting the other linear polarization. Lastly, one or more waveplates are disposed in the optical path between the polarizer and the parabolic mirror. The waveplates have opposing segments each having axes which are antiparallel to each other for recycling the reflected linear polarization by converting it to the transmitted polarization.

Abstract: A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation enters the initiating device's architected logic queue to be issued on the system bus. The flag remains set even after the architected logic queue is drained, and is reset only when a synchronization instruction is received from a local processor, providing historical information regarding architected operations which may be pending in other devices. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty.

Abstract: A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: Method and system aspects for monitoring computer system operations are provided. A computer system including a processor, the processor supporting firmware and a running operating system, and a service processor coupled to the processor, is monitored by initiating surveillance of the computer system in the firmware when an architected function occurs in the operating system. Monitoring additionally includes providing a pulse indicator from the firmware to the service processor and determining a status of computer system operations with the service processor based on a frequency of the pulse indicator.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A computing system that incorporates the invention includes a host processor which is coupled to a memory subsystem via a first bus system, a controller device and a second bus system. The controller device includes memory for storing plural Scripts for replay to the host processor, for instance, via the second bus system. A Script is an instruction set used to execute operations on a controller device. Each Script includes one or more addresses where either message or status data (or other operational data) can be found which is to be inserted, prior to dispatch of the Script. During operation of the computing system, the memory subsystem is caused, as a result of its operation, to issue an instruction to the controller device to dispatch a Script to, for instance, the host processor. The controller device responds by accessing the required Script, playing the Script which results in accesses to locally stored operational data for inclusion into the Script.

Abstract: Disclosed is a system for notifying a user of account activity, such as a withdrawal from a savings or checking account. A computer system maintains information on financial accounts and electronic user contact information for at least one of the financial accounts, such as a telephone number, e-mail address or pager number. Information on a transaction with respect to one of the financial accounts is received and processed. The computer system then processes the information on the transaction and generates an electronic message providing information on the transaction. The user contact information for the financial account involved in the transaction is processed. The message is then electronically transmitted to the location identified by the user contact information for the financial account.

Abstract: Systems, methods and computer program products for sharing state information between a stateless server and a stateful client are provided. A client request to perform an action on the server is accompanied by an encrypted token which contains state information. The server receiving the client request decrypts the token using a symmetric key generated from variable data. The server verifies that the received token is valid and uses the state information contained therein to perform the requested action. The server also provides clients with encrypted tokens using a symmetric key generated from variable data.