Abstract: A group editor has a communication unit, an internal clipboard control unit, a system clipboard control unit, and an internal clipboard. The group editor operates to share the results of input and editing operations among a plurality of computer systems. An operating system clipboard is also provided. The system clipboard and the internal clipboard are linked by the communication unit, internal clipboard control unit, and system clipboard control unit, whereby the user only needs to perform an operation on one clipboard regardless of whether copy and paste between different applications or copy and paste within the same group editor, are performed. Therefore, usability increases, and traffic of the network is decreased.

Abstract: Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A keyblock is shown for use in a computer cage having an interior and a guide rail for guiding a logic-card book into position within the interior. The keyblock is installed within a cage guide opening provided at an end of the guide rail within the cage interior by means of a downwardly projecting dart which is received within the opening in snap-fit fashion. Locating pins on the keyblock lower surface properly position and align the keyblock within the cage guide opening. Contoured regions on the keyblock upper surface engage and lead-in a complimentary surface located on the logic-card book being received within the cage interior. One or more slots provided between selected contoured regions provide a coded pattern which matches a pattern provided on the desired logic-card book to be received in a predetermined position within the cage interior.

Abstract: In a token ring network a periodic recirculating frame having a plurality of information carrying slots and a header section is used for enabling a plurality of telephone stations to exchange information carrying signals. The header is provided with a token which can assume one of three states. In the first state FF, a telephone station wanting to make a call, changes the token to the second state 00 and inserts call establishment information in the header. A server station also connected in the ring detects the second state as a request to establish a connection from and to a station specified in the header. The server changes the token to the third state AA and inserts a slot assignment in the header. All stations receiving a frame with a token in the third state examine the header. The calling station implies confirmation of the requested connection and the called station is made aware of the call and the identity of the caller.

Abstract: A method for determining optimum segment size in a data transmission system which uses a communications network that imposes a Maximum Transferable Unit (MTU) data packet size. The total cost (host processing plus transmission) is determined for a segment equal in size to the MTU. This cost is sequentially compared to the total cost of segments which are integer incremented multiples of the MTU. When the comparison indicates that the segment which is an integer multiple of the MTU exceeds the total cost of transferring the segment equal in size to the MTU, the comparison is terminated and the segment size is set equal to the segment size of the next prior comparison.

Abstract: A server-based application intercepts an initial request for access to documents which may contain imbedded references to linked information. A request is made from the server to the actual location of the requested document as it is found on a network (e.g. WORLD-WIDE WEB, INTERNET, etc.). The document is retrieved into the server and parsed to discover all imbedded addresses contained therein. The server then replaces each imbedded address with its own address plus the original imbedded address such that all future references to the imbedded information will be supplied by the server. Additional linking information, functions and/or environment escape information may then be prepended and/or postpended to the requested document independently through the server.

Abstract: A method, apparatus and article of manufacture for compensating for carrier frequency error is disclosed. An FM signal is received from an antenna and the received FM signal is provided to receiver. The receiver takes the FM signal at the carrier frequency and outputs a baseband signal. This baseband signal is then processed by a DSP which provides carrier frequency compensation and decoding to produce a data stream that a microprocessor provides to a host device. Frequency differences between the FM carrier frequency and the frequency used to demodulate the FM signal can shift the DC bias level of the baseband signal. The DSP compensates for such frequency difference by using a receive compensation value and applying it to each received signal sample. When transmitting, data to be transmitted is provided from the host device to the DSP via a microprocessor.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.

Abstract: A reference storage process populates a data structure so that the data structure contains all of the molecular structures and/or rigid substructures in the database classified according to attributes of tuples. In a preferred embodiment, the tuples are derived from sites (e.g. atomic sites) of the molecular structures and the attributes can be derived from geometric (and other) information related to the tuples. The attributes are used to define indices in the data structure that are associated with invariant vector information (e.g. information about rotatable bond(s) in skewed local coordinate frames created from tuples). These representations are invariant with respect to the rotation and translation of molecular structures and/or the rotation of substructures about attached rotatable bond(s). Accordingly, the invariant vector information is classified in the data structure with the respective tuple attributes in locations determined by the index derived from the respective tuple.

Abstract: A processor and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units for executing instructions, including a branch processing unit for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

Abstract: An apparatus capable of housing PC cards including a PC card with a connector and PC card guide, a housing having an insertion opening for inserting the PC card and a circuit board mounted in the housing. The connecting direction between the PC card and the circuit board is perpendicular to the insertion direction of the PC card. The apparatus further includes guides arranged on the housing having two cam plates which are separated by spacers and supported by a shaft. Each cam plate has a continuously recessed guide path for guiding the PC card. The guide path has a guiding portion and a stop portion wherein the transition of the pivot pin from the guiding portion to the stop portion causes a defined rotation of the plug-in package about the pivot point wherein the plug-in package is rotatably arranged at the pivot point. This allows the PC card to make a pivot motion in order to accomplish the connection between the plug-in package and the circuit board.

Abstract: A method and apparatus for acoustic signal processing of speech recognition, the method comprising the following components: 1) Decompose each syllable into two phonemes of comparable length and complexity, the first one being a preme, and the second one being a toneme; 2) Each toneme is assigned a tone value such as high, rising, low, falling, and untoned; 3) No tone value is assigned to premes; 4) Pitch is detected continuously and treated the same way as energy and cepstrals in a Hidden Markov Model to predict the tone of a toneme; 5) The tone of a syllable is defined as the tone of its component toneme.

Abstract: Lead On Chip ("LOC") leadframe designs for thin, small-outline packages having improved configurations of leadframe members are provided. The LOC leadframes comprise a bus bar, having at least one distribution finger, and a plurality of lead fingers arranged in such a manner that jump-over is eliminated, thus increasing the reliability of the package.

Abstract: A system for overcoming force which inhibits movement of a data storage device is provided. An actuator is mounted at the perimeter of a circular data storage device and has a pivoting armature. The armature is mounted to pivot into contact with the perimeter of the storage device thereby initiating movement thereof and overcoming any force inhibiting the movement thereof, and to pivot out of contact with the perimeter of the storage device to allow for subsequent rotation thereof.

Abstract: In a computer environment which provides support for compound documents composed of multiple parts, a technique is provided for linking parts which rely on common data so that updating the common data in one part updates the common data in the linked parts. The parts are preferably object oriented in nature, and the linking is performed automatically.

Abstract: In an image acquisition system, which produces at least one image, each of which is scorable with reference to at least one image quality criterion, a control system is provided for optimizing the image quality criterion. Typically, the image quality criterion is at least in-part established by an exposure parameter. When considered as an apparatus, the present invention includes a number of components which cooperate together to automatically and continually adjust the value of the exposure parameter to optimize the image quality criterion. An image acquisition means is provided to obtain one or more acquired images under selected exposure characteristics. A transform system is provided for receiving the one or more acquired images and developing an energy distribution map, or histogram, of at least a portion of the one or more acquired images.

Abstract: An apparatus and method for reading an information signal from a magnetic storage medium using a magnetoresistive (MR) element, modifying the signal such that a thermal component of the signal representing a thermal response of the MR element is degraded, and altering the modified signal to produce a restored thermal signal substantially representative of the thermal component of the signal read from the storage medium. The information signal induced in the MR element is communicated from the MR element to an arm electronics (AE) module having a highpass filtering behavior. The AE module passes content of the information signal other than the thermal component content, thereby degrading the thermal component of the information signal. An inverse filter, implemented using an infinite impulse response (IIR) filter, receives the highpass filtered signal from the AE module and produces a restored thermal signal substantially representative of the thermal component of the information signal.

Abstract: A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

Abstract: A method and system for managing utilization of licensed program within a distributed data processing system having a number of local systems which minimizes the amount of network communication traffic required for such management. Each permitted use of a licensed program by a distributed data processing system is indicated by a use token which may be transferred to selected systems throughout the distributed data processing system. These use tokens are then periodically redistributed throughout the distributed data processing system in response to a requested usage by a particular system within the distributed data processing system. A use token transferred to a particular system is then maintained at that system upon completion of the usage until such time as a request for usage of the licensed program requires transfer of the use token to another system.

Abstract: A two stage latch sensing circuit provides high performance at low power in static random access memory (SRAM) devices. The first stage takes the small signal development from the array bitlines which is passed to the sense latch through bit-switches and amplifies it. P-type field effect transistor (PFET) devices are used to drive a precharged high, low-signal swing read data bus. The second stage sense latch amplifies the signal from the read data bus, thereby providing a full level swing to the outputs.