Abstract: An apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.

Abstract: In a pattern-matching network, such as a RETE, elapsed time for successive pattern matching operations is reduced by selectively priming predetermined ones of pattern-matching nodes, such as beta nodes, by caching stabilized computed delta input or argument values derived from ones of the predecessor nodes that appear not to change during the conduct of one of the tests in the node. The computed argument value caching occurs in an argument storing portion of any test to be conducted using a cached argument value. At any node, different tests may or may not be able to used cached argument values.

Abstract: In a data processing system including a relatively large, page-formatted memory, memory control functions are distributed over a plurality of microprocessors connected in an array with each microprocessor controlling a respective area of the large memory. Upon overflow of its assigned memory area, a microprocessor may "borrow" free memory space assigned to one of its neighbors in the microprocessor array. Memory control functions with respect to different areas in the memory can effectively be performed in parallel, thus improving the operating efficiency.

Abstract: Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.

Abstract: The dissolution rate in alkaline developer solutions of image-wise exposed photoresist systems based on diazoquinone sensitized polyamic acid is reduced to prepare relief images of fine line resolution by reducing the acidity of the polyamic acid prior to exposure.

Abstract: A method for providing engineering changes to LSI PLAs. One or more additional input lines, output lines, and/or product terms are provided in the overall mask set, however, logically unconnected to the rest of the PLA, which is designed to provide the desired PLA function. The additional lines and terms are provided so as to be able to be connected to the PLA, and provide additional personalization by changes to the contact mask and masks for subsequent process steps to contact. The invention may be incorporated in an existing PLA macro assembler system. By simply redefining certain cells the additional devices may be incorporated through those redefined individual cells. Thus, the invention is relatively easy to retrofit to existing PLA macro assembler systems.

Abstract: Thin-film electrical circuits are interconnected by a process comprising the steps of partially ablating the existing thin-film conductor at the connection point(s) by means of a pulsed laser and depositing a thin-film metal interconnection over the desired area, which includes the area(s) of the existing thin-film circuit that were exposed the pulsed laser.

Abstract: A method of controlling the unauthorized disclosure of classified data that is used to describe an event that has been calendared in an electronic calendaring application of an interactive information handling system in which the calendar owner assigns a security classification to an event as it is being calendared. The classification assigned is pre-established by an information security protocol that is either unique to the calendar function or a more comprehensive information security system for the organization. The security classes are pre-established by the system. When the calendar data is presented in a format that allows event descriptions to be readable such as when a day calendar is viewable on the display terminal or in a printed copy, an overall security lable is displayed and printed out when the display is converted to hard copy. The period covered by the security label generally corresponds to the period that is selected for viewing.

Abstract: An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor.

Abstract: Encoding method for data to be recorded on optical disks using the pit-per-transition technique or return-to-zero techniques whereby the characteristics of the encoded bits produce a stable, low frequency spectral notch and minimum interference with associated focus and tracking servomechanisms. RLL (d,k) code words are selected so that the ratio of the lengths of pits and lands approximate some nonzero fraction less than one-half which depends on the (d,k) code employed. For example, a fraction of 1/3 is appropriate for RLL (2,7).

Abstract: A method for making a thin film magnetic head in which the pole tips are trimmed to a predetermined width prior to the completion of the magnetic yoke structure. The thin film magnetic head is produced through deposition of the first magnetic layer in two stages, through deposition of the coil, the insulating material for the coil and through deposition of the second magnetic layer. The thin film head is then masked by a photoresist mask having openings to expose specific parts of the pole tip region, and an ion milling operation is used to etch the head assembly to form pole tips having a predetermined width. The shaping layer for the second magnetic layer is then deposited to complete the magnetic yoke structure.

Abstract: A flat cable bus with fan-out patterns which provide equal length wires to eliminate clock skew is disclosed.

Abstract: A protective circuit for a magnetoresistive (MR) element having a first and a second terminal in which a first current source is coupled to the first terminal of the MR element to produce a bias current through the MR element and a second current source is coupled to the second terminal of the MR element to produce a reference current. Circuit means coupled across the MR element senses the center potential of the MR element substantially midway between the first and second terminals, and a feedback circuit responsive to the sensed center potential is coupled to adjust the current output of the first current source to maintain the center potential to a selected reference voltage to protect the MR element from short circuits to a conductive area of the magnetic recording medium.

Abstract: A multilayered ceramic (MLC) substrate having embedded and exposed conductors suitable for mounting and interconnecting a plurality of electronic devices exterior thereof. The horizontal planar conductors comprise substantially a plurality of solid, non-porous, homogeneous metal patterns, whereas the vertical interplanar connection conductors are substantially porous metal conductors that are formed by methods such as screening. The process to form the MLC substrate involves forming a pattern of solid, nonporous conductors to a backing sheet having a release layer, then transferring the pattern to a ceramic green sheet. Zero X-Y shrinkage sintering processes allow the MLC substrate and solid metal conductors to be densified without distortion of the solid metal patterns or the ceramic.

Abstract: The parity generation circuit which is disclosed takes advantage of a property of the parity of a number before and after it has been incremented. This is characterized as the parity toggle property and it allows parity generation to be done on the most significant bits of an adder before the carry input to these most significant bits has been generated from the least significant bit portion of the sum produced by the adder. The final parity for the entire sum output of the addition process is adjusted quickly when the carry into the most significant bits of the sum becomes available from the least significant bit portion of the sum output. The parity toggle property of the invention allows for the quick adjustment of the parity without incurring the undue delay of waiting for the production of the carry output from the low order sum before commencing computations with the high order sum.

Abstract: The saturation voltage of a photoconductor used in a discharged area development (DAD) reproduction device is used to control and maintain the voltage vectors that are associated with (1) the photoconductor's fully charged background area, (2) the development electrode voltage at the reproduction device's developer station, (3) the photoconductor voltage in areas that are occupied by image characters having a small surface area, and (4) the photoconductor voltage in a test patch area that is associated with a toner concentration control network having a toner patch sensor. These electrstatic parameters are periodically adjusted, to compensate for changes in the operating characteristics of the photoconductor and the imaging station.

Abstract: A circuit to function as an interface between larger test instrumentation having a high capacitance, including connecting leads, and a small, low current, monolithic chip device. This interface circuit has no internal control logic, is capable of transactions in both directions and is small itself, thereby fitting close to the monolithic chip device and reflecting a relatively low capacitance load to the chip.The interface circuit includes an input buffer amplifier connected to provide a driving voltage to drive the test instrumentation in response to a voltage from the small monolithic chip device, and a sensing resistor is connected with the input buffer amplifier so that their combined equivalent resistance value is substantially equal to the resistance reflected by the test instrumentation. An operational amplifier is connected to drive a small monolithic chip device in response to a voltage across the sensing resistor that is developed by the test instrumentation.

Abstract: A cross-point switching array in which each cross-point of the array is controlled by the output of a first memory. Each first memory is associated with a second memory. The second memories can be sequentially set by a single controller while the cross-point connections are maintained according to the first memories. The contents of all second memories are concurrently loaded into the associated first memories to simultaneously reconfigure the cross-point array.