Abstract: The system provides both electronic signature and message verification with a minimum of excess coding information on an instantaneous basis and is easily restartable in a store and forward environment. The system is based on the concept of a vault or central authority. The vault is in essence a physically secured Authenticator designed as a hardware automation which is not under control of any operating system. The system is a terminal based network wherein all terminals or users may communicate directly or through a central CPU. All secure electronic signature verification transactions must be transacted through the central facility which includes said vault. The vault and all terminals include an identical key-controlled block-cipher cryptographic facility wherein each user at a terminal has access only to his own key and wherein the vault has access to all user keys.

Abstract: This invention details a baseband bipolar pulse signaling technique employing only two wires for simultaneous bi-directional communications. A first polarity of pulses is utilized for communication of traffic in one direction; traffic in the return direction utilizes pulses of the opposite polarity. Each end of the communication link has both a sender and a receiver. One sender arbitrarily transmits only positive pulses; the receiver at this end of the system will recognize only negative pulses. The inverse set of conditions is enforced at the opposite end of the link. Means are included for synchronizing the application of pulses to the link at the other end in response to the receipt of pulses at that end to avoid overlap of receive pulses at the originating end of the line.

Abstract: A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.

Abstract: Sheet-like articles, such as paper, entering one or more support trays are aligned in one or more vertical stacks by a pair of rotating drive devices positioned vertically and adjacent to opposite sides of the support trays. The rotating drive devices include a plurality of resilient flaps mounted to a support member. The flaps are configured to reach over a stack of sheets thereby contacting a sheet on its top surface as well as on its edge.

Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Abstract: A computer system having two processors and storage where storage is segmented so as to permit simultaneous access by the two processors with the address path of one processor being limited to a particular segment of storage so as to eliminate contention in other segments. One processor can address all segments of storage and place processed data into and retrieve data from the segment of storage accessible by the other processor. This eliminates the need for cycle stealing because the other processor can access processed data or store data while the one processor simultaneously accesses another segment of storage. Storage contention is resolved on the basis of addressing. If both processors are simultaneously trying to address the same segment of storage, the processor which can address all segments of storage is granted the access.

Abstract: An apparatus for measuring the surface potential and impurity concentration in a semi-conductor body by monitoring the current flowing in a semiconductor body when the body is biased with a ramp voltage above its flat band voltage and summing the monitored current with the ramp voltage biasing the body. The apparatus provides direct measurement of surface potential and impurity concentration in a semiconductor structure and is especially useful in metal insulator semiconductor (MIS) structures.

Abstract: Plasma oxidation of the surface of a substrate which surface does not face towards the plasma is achieved by placing the substrate perpendicular to the plasma in a region at a pressure of at least about 10 mtorr.

Abstract: The object of this invention is to purge any entrapped air from the ink cavity (17) and nozzle orifice (15) of the print head (10) of a drop-on-demand ink jet printer. Purging is accomplished automatically as a part of the start up operation and also if, during operation, the velocity V.sub.s of the ink droplets (26), as sensed by a sensor (41), drops below a preselected reference value V.sub.r.The print head comprises a tubular piezoelectric transducer (11). The transducer is energized with a series of pulses for a preselected short time period and at a repetition rate substantially equal to a resonant frequency of the ink cavity. This effectively purges any entrapped air from the ink system. Except during purging, the transducer operates asynchronously in drop-on-demand mode in response to discrete binary print signals.

Abstract: Heat is removed from a Large Scale Integrated Circuit semiconductor package via a thermal conductive path including a thermally conductive liquid. The integrated circuit chips are flip chip bonded to a substrate having a printed circuit and raised contact pads serving to interconnect contact areas on the chip. A metal, ceramic (or combination thereof) cover engages the perimeter of the substrate and encloses the chips (or chip). The thermal liquid is contained within the cavity define by the cover and substrate. The chips (or chip) and the flip chip connections are protected from contamination and the deleterious effects of the thermally conductive liquid by a parylene film enveloping same. Additionally, back side bonded (beam lead) integrated circuit chips will have an enhanced heat transfer path by incorporating liquid metal and a protective coating of parylene.

Abstract: A two-level storage hierarchy for a data processing system is directly addressable by the main processor. The two-level storage includes a high speed, small cache with a relatively slower, much larger main memory. The processor requests data from the cache and when the requested data is not resident in the cache, it is transferred from the main memory to the cache and then to the processor. The data transfer organization maximizes the system throughput and uses a single integrated control to accomplish data transfers.

Abstract: A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit.

Abstract: This is an electronic storage array used in data processing systems for the storage of information in the form of binary bits. The storage is fabricated in integrated circuit form, typically on a semiconductor chip, each storage cell being contained within a single isolated zone formed in the semiconductor chip. Each storage cell is DC stable and operates on a conductivity modulation principle, i.e. a cell conducts when it stores a binary "1" and the conductive state is maintained by conductivity modulation of an element of the cell, and the cell is non-conducting when storing a binary "0". In its most basic form, each cell includes at least two resistors formed in series in a P type semiconductor region. At least one of the resistors, formed in a lightly doped portion of the P type region, is a variable resistor having both high and low values of resistance. The high value of resistance is changed to a low value of resistance by injecting electrons from a proximate N type semiconductor region.

Abstract: Apparatus and method for rework dressing a chip site on a substrate prior to rejoining a chip by solder reflow. A compliant mask is aligned and placed on the substrate so that remnant solder columns on chip site pads protrude through holes in the mask. A brush mechanically removes excess solder and dresses any remaining solder columns to uniform shapes and volumes.

Abstract: System and method for determining whether a first operation is responsive to a controller. A second operation, whose successful functioning depends on the successful functioning of the first operation and which produces a sensible result, is initiated while the first operation is inhibited by the controller. Sensing that the second operation is producing a result indicates that the first operation is not responsive to the controller. A further test is provided to determine whether the second operation is functioning properly.

Abstract: This switch monitoring circuitry is particularly applicable to switching circuitry for operating a bipolar load device, frequently an inductor, on a source of direct current with four switches arranged to alternate the polarity of potential across the load device in a predetermined periodicity. Such circuitry often is arranged with diode devices individually connected across the switches, especially where the load device is an inductor. The monitoring circuitry specifically described comprises basic logical circuitry having coincidence gating circuits for activating status indicating circuitry; or for controlling associated circuitry for protecting or for compensating the switching circuitry; or for alarming operating personnel of malfunctioning switches.

Abstract: A copy production machine, or other semiautomatic operator-involved machine, logs operations data and error data during normal operations into a nonvolatile store. Logging is categorized for facilitating diagnostics and maintenance of the machine. During a maintenance mode, log scanning methods enable efficient retrieval of the logged data via a keyboard entry system plus manual actuation of other switches used for other purposes during the normal copy production.

Abstract: A storage system, such as a read only memory, is provided which includes field effect transistors each having first and second spaced apart diffusion regions of a given conductivity and a gate electrode, with at least one of the two diffusion regions of selected transistors having a third diffusion adjacent to one of the first and second diffusion regions under the gate electrodes to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions is sensed. During a second period of time the voltage is applied to the second diffusion and the current flow between the first and second diffusions is again sensed.

Abstract: A patient's own heart is used as a voltage source for measurement of EKG electrode impedance. The amplitude of an EKG signal obtained while the EKG electrodes are shorted together with an impedance is compared to the amplitude of an EKG signal obtained under identical conditions except that the impedance short is not present. The value of the inter-electrode impedance is then equal to one less than the ratio between the unshorted amplitude and the shorted amplitude times the value of the shorting impedance. In a preferred embodiment, the value of the shorting impedance is made equal to the maximum permitted inter-electrode impedance. Then, if the amplitude of the EKG signal taken from a patient decreases upon temporary insertion of the impedance short to a value less than half of the EKG amplitude obtained without the impedance short, the inter-electrode impedance is too high.

Abstract: Communication control functions are performed by an integrated adapter implemented as microcode resident in host CPU storage. The integrated adapter shares a common high speed bus with other CPU facilities. A high speed bus adapter provides an interface between the common high speed bus and low speed line adapters. Communication controlling commands and register structures are described.