Abstract: A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor.

Abstract: Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing.

Abstract: A server enclosure having a plurality of panels abutted to one another and constrained by a connector having a channel and at least one aperture. Each respective panel has at least one perpendicular portion being perpendicular to a face of the respective panel and adjoining a perimeter of the respective panel. Connectivity media coincident to the aperture can affix at least two panels and a connector to one another.

Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Abstract: A storage appliance system is disclosed which may include at least one application server for locally executing an application, and one or more storage servers in communication with the application server for I/O transmission therebetween. Also disclosed are an application server, a method, and a computer program product.

Abstract: A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.

Abstract: Examples of techniques for processing model changes are described herein. A method includes generating, via a processor, a change log in a model. The method also includes detecting, via the processor, a change to a model element of a model package in the model. The method further includes storing, via the processor, the detected change as a change item in a topic of the change log.

Abstract: According to one aspect of the present disclosure a method and technique for allocating and reserving virtualization-based resources is disclosed. The method includes: receiving, by a virtualization-based resource management system, a reservation request to reserve a set of computing resources; dynamically allocating the set of computing resources to the reservation request; assigning a key to the allocated set of computing resources; and maintaining the allocated set of computing resources in a reserved state until a utilization request is received to utilize the allocated set of computing resources, the utilization request including the key.

Abstract: Backfill scheduling for embarrassingly parallel jobs. A disclosed method includes: receiving an initial schedule having a plurality of jobs scheduled over time on a plurality of nodes, determining that a first job can be split into a plurality of sub-tasks that can respectively be performed in parallel on different nodes, splitting the first job into the plurality of sub-tasks, and moving a first sub-task from its position in the initial schedule to a new position to yield a first revised schedule.

Abstract: An approach is described for routing data to a plurality of output terminals via a integrated switch router including a crossbar switch having both a crossbar and a plurality of crossbar bypass lines. Whereas the crossbar may connect each input of the crossbar switch to each output of the crossbar switch, each of the plurality of crossbar bypass lines may connect a single input of the crossbar switch to a corresponding single output of the crossbar switch. According to such approach, a replicated copy of a multicast packet may be forwarded to an output terminal via a crossbar bypass line in parallel with other data forwarded via the crossbar, thus increasing integrated switch router bandwidth.

Abstract: Reducing energy usage by a monitor includes a map manager between a monitor interface and a processor that divides a display area of a monitor into areas and stores display information in a staging area. The map manager distinguishes an active window selected by a user from the remainder inactive, unselected areas of a display, and further determines a used subset of areas within the active window distinguished from the remainder unused areas as a function of a user preference. Accordingly, the map manager drives the monitor at each of the used area active window areas with the processor display information stored in the staging area at a normal luminance specified by the processor display information, and at each of the remainder unused, inactive and unselected areas of the total display area at a reduced luminance lower than the specified normal luminance.

Abstract: In an approach for preventing the modification of an email by the recipients of the email, a processor receives an indication that an email message is composed. A processor receives an indication that modification of contents of the email message, by one or more recipients of the email message, is to be prevented. A processor converts the contents of the email message from editable text to a non-editable format. A processor sends the converted email message to a recipient.

Abstract: A mobile terminal accesses global DNS server using a URI of a resource in an intranet. The global DNS server returns an IP address of an intranet domain access resolver. The mobile terminal connects to the intranet domain access resolver using the IP address and transmits a portion of the URI. The intranet domain access resolver encodes information received from the mobile terminal and generates a new URI and returns the new URI to the mobile terminal. The mobile terminal uses the new URI to access the intranet via a gateway based on an information item obtained by decoding the original URI.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: Responsive to a user marking a region, identifying each object present in the region and storing an indication of the region and identified object(s), preserving a positional relationship in which the identified object(s) are displayed in the region; upon detecting that the identified each object is not displayed in the window, displaying the region as a sub-window located at the periphery, the displayed sub-window containing the identified each object in the preserved relationship; and upon detecting that the region subsequently shifts into the window, deleting the sub-window. Responsive to a user selecting a displayed object and marking a displayed region, storing an indication of the region and the object; while the object of the region is not displayed in the window, displaying a sub-window in a periphery of the window, the sub-window displaying the object in the region; and automatically closing the sub-window in response to the object being again displayed in the window.

Abstract: A method is provided for forming an integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs. Initially, a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge) is formed. The SiGe layer is recessed to form a recessed SiGe layer in the n-type region while leaving an intact SiGe layer in the p-region. A Si layer consisting essentially of Si is formed on the recessed SiGe layer. The Si layer and recessed SiGe layer are patterned to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion. The intact SiGe layer in the p-region is patterned to form an intact SiGe fin. The recessed SiGe fin portion in the n-region is selectively oxidized utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.

Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Abstract: Systems and methods for optimizing resolution of an electronic display device are disclosed. A computer program product for optimizing display resolution of an electronic device includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computing device to cause the computing device to: detect the presence of at least one user; determine an identity of the at least one user; obtain, from a user data storage module, personalized optimal resolution data of the at least one user; and adjust the resolution of the electronic device display based on the personalized optimal resolution data.

Abstract: A number of synchronization objects simultaneously usable during runtime by a group of threads within a multi-threaded execution environment is predicted by a processor that manages synchronization object allocations within the multi-threaded execution environment. A synchronization object pool is allocated with the predicted number of synchronization objects, each initialized with a deployment state of undeployed and an acquisition state of unlocked. Over time, the deployment state is changed between deployed and undeployed in response to requests by threads to deploy and undeploy the synchronization objects. The acquisition state is independently controlled as the synchronization objects are acquired and released by the threads. The allocated number of synchronization objects within the synchronization object pool is adjusted during the runtime in response to determined deployment rates of the allocated number of synchronization objects.