Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

Abstract: Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request.

Abstract: The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

Abstract: Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.

Abstract: A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.

Abstract: Methods, apparatuses, and computer program products for collective operation management in a parallel computer are provided. Embodiments include a parallel computer having a first compute node operatively coupled for data communications over a tree data communications network with a plurality of child compute nodes. Embodiments also include each child compute node performing a first collective operation. The first compute rode, for each child compute node, receives from the child compute node, a result of the first collective operation performed by the child compute node. For each result received from a child compute node, the first compute node stores a timestamp indicating a time that the child compute node completed the first collective operation. The first compute node also manages, based on the stored timestamps, execution of a second collective operation over the tree data communications network.

Abstract: A method for processing a resource access request in a network based on a software defined network (SDN) protocol includes receiving a resource access request forwarded by a first SDN switch in the network, wherein there exists no forwarding rule matching the resource access request in the first SDN switch; obtaining, according to the resource access request, resource server information of a resource server where the requested resource is stored, wherein the resource server is located in the network; generating a forwarding rule corresponding to the resource access request according to the resource server information; and sending to the first SDN switch at least one portion of the forwarding rule corresponding to the resource access request, so that the first SDN switch forwards the resource access request according to the at least one portion of the forwarding rule.

Abstract: Optimization of mobile telecommunications service during a power outage at one or more base stations, wherein optimization includes identifying one or more of a plurality of base stations to which non-emergency electrical power has been interrupted; determining an initial number of users in areas corresponding to the one or more of the plurality of base stations; generating a user location probability model and a user call probability model; scheduling initial battery power operation for the plurality of base stations; monitoring user calls and user movement after the battery power operation has started; updating the user location probability model and the user call probability model based on the monitoring; and updating battery power operation scheduling for the plurality of base stations.

Abstract: A method identifies anonymized parties in a transmitted communication. A sender replaces one or more communication party identifiers in control data within a communication with one or more anonymized identifiers before transmitting the communication to one or more recipients of the communication. A recipient receiving the communication searches a local lookup table by an anonymized identifier for a corresponding non-anonymized identifier which identifies a party of the communication. In response to identifying a corresponding non-anonymized identifier, the recipient then replaces the anonymized identifier with the corresponding communication party identifier and presents the recipient with the non-anonymized identifiers within the communication.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

Abstract: Embodiments are directed to a method of accessing a data frame. The method includes, based at least in part on a determination that the data frame spans first and second memory blocks, and further based at least in part on a determination that the processor has access to the first and second memory blocks, accessing the data frame. The method includes, based at least in part on a determination that the data frame spans the first and second memory blocks, and based at least in part on a determination that the processor has access to the first memory block but does not have access to the second memory block, accessing a first portion of the data frame that is in the first memory block, and accessing at least one default character as a replacement for accessing a second portion of the data frame that is in the second memory block.

Abstract: Embodiments relate to interacting with a collection of user opinion documents associated with a topic. One aspect includes obtaining opinion data for the collection of opinion documents associated with the topic. The opinion data includes one or more features discussed in the opinion documents, one or more key phrases included in each feature, one or more text snippets included in each feature, and at least one sentiment expressed in each text snippet. A visual interface is provided in which a feature summary view of the opinion documents acts a top level of a navigational hierarchy. The visual interface allows user navigation from the top level to a lower level of the navigational hierarchy in order to display more details about a text snippet, as compared to the feature summary view, while continuing to provide the feature summary view.

Abstract: According to one exemplary embodiment, a method for VIOS failover in an environment with a physical storage adapter is provided. The method may include assigning the physical storage adapter to a first VIOS, wherein the physical storage adapter has I/O connectivity to at least one storage device. The method may include configuring a first I/O path between the first VIOS and a second VIOS. The method may include configuring a second I/O path from a client partition to the first VIOS, wherein the second I/O path is set as a primary I/O path. The method may include configuring a third I/O path from the client partition to the second VIOS. The method may include determining the first VIOS is inaccessible. The method may include unassigning the physical storage adapter from the first VIOS. The method may include assigning the physical storage adapter to the second VIOS.

Abstract: A method and system for achieving emotional text to speech. The method includes: receiving text data; generating emotion tag for the text data by a rhythm piece; and achieving TTS to the text data corresponding to the emotion tag, where the emotion tags are expressed as a set of emotion vectors; where each emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories. A system for the same includes: a text data receiving module; an emotion tag generating module; and a TTS module for achieving TTS, wherein the emotion tag is expressed as a set of emotion vectors; and wherein emotion vector includes a plurality of emotion scores given based on a plurality of emotion categories.

Abstract: Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

Abstract: A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

Abstract: A method for clustering images includes acquiring initial image data including a scene of interest. A 3D model is constructed of the scene of interest based on the acquired initial image data. Additional image data including the scene of interest is acquired. The additional image data is fitted to the 3D model. A line-of-sight of the additional image data is estimated based on the fitting to the 3D model. The additional image data is clustered according to the estimated line-of-sight.

Abstract: The invention is notably directed to a scanning probe sensor for a scanning probe microscope. The scanning probe sensor comprises a probe tip having a ferromagnetic fluid and a magnetic field generator adapted to generate a magnetic field acting on the ferromagnetic fluid. Furthermore, a sensor controller is provided and configured to control one or more parameters of the magnetic field generator, thereby controlling the shape of the fluid. The invention further concerns a related scanning probe sensor, a related method and a related computer program product.

Abstract: A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.

Abstract: Aspects relate to an integrated system that is electrically powered. The integrated system includes a circuit board and a photovoltaic device. The circuit board includes one or more on-board electronic components and an upper surface configured as a substrate. The photovoltaic device is integrally deposited on the upper surface of the circuit board and electrically connected to the one or more on-board electronic components, wherein the upper surface of the circuit board is a photovoltaic device substrate.