Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: A method, computer program product, and system for enabling parallel processing of an XML document without pre-parsing, utilizing metadata associated with the XML document and created at the same time as the XML document. The metadata is used to generate partitions of the XML document at the time of parallel processing, without requiring system-intensive pre-parsing.

Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.

Abstract: Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.

Abstract: A method, apparatus and computer program product for controlling access to host access credentials required to access a host computer system by a client application is provided. The host access credentials are stored in a restricted access directory. The method comprises authenticating directory access credentials received from a client application. The authenticated client application then requests the host access credentials and a determination as to whether the authenticated client process is authorized to access the requested host access credentials, and, if authorized, these are provided to the client application.

Abstract: A method and apparatus for removing a pad adhesively secured to a platen. The apparatus includes a barrel assembly having a clamp assembly fixedly attached to a perimeter of the barrel assembly; a rotatable handle assembly nested within the barrel assembly; and a ratchet assembly nested between the handle assemble and the barrel assembly the ratchet assembly configured to engage the rotatable handle assembly.

Abstract: In one embodiment, an addition of an identifier to a contact list can be detected. The identifier can identify an entity in a first collaboration system. Data can be searched to find a different identifier that identifies the entity in at least a second collaboration system. The different identifier can be added to the contact list.

Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.

Abstract: A fail-to-wire (FTW) module that preserves a primary data path connection from an upstream computer to a downstream computer if there is any kind of failure in a breakout data path to a breakout system. The FTW module provides switches between the incoming data network data and the breakout system such that when the breakout system encounters a failure, the switches are de-activated to bypass the breakout system. The switches in the FTW module are activated by a system health signal from the breakout system. The breakout system can be serviced without interrupting the data network connections since the FTW module can be extracted from the failed breakout system with data network connections intact. The FTW module is preferably a compact modular element that fits within the breakout chassis and is easily inserted and removed from the breakout system during servicing operations.

Abstract: For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations. A total number of I/O operations to be awoken at each of an iterated instance of the waking is limited.

Abstract: The disclosure is directed to email addressee verification. A method in accordance with an embodiment includes: obtaining an email message including at least one email address; evaluating each email address of the email message against at least one email rule, and assigning a score to each email address based on the evaluation; and comparing the score assigned to each email address to a threshold, and flagging any suspect email address based on the comparison.

Abstract: A system and computer program product for assigning runtime artifacts to software components. Source code and metadata are extracted from a library, where the metadata includes a component membership for the source code. A compile unit is formed from the extracted source code and metadata. Runtime artifacts are produced from the compile unit or an element derived from the compile unit. Each runtime artifact is interrogated to determine the defined component for each runtime artifact. The determined component is recorded.

Abstract: A method for priority buffering of trace data in a computing system includes receiving instances of trace data by a priority assignment module, the trace data being generated by events that occur during execution of computer software in the computing system; assigning a priority to each instance of trace data, wherein the priority is assigned based on the event that generated the instance of trace data; and inserting the instances of trace data into a plurality of priority buffers based on their respective assigned priorities.

Abstract: A method, system, and computer program product for collaborative and integrated intellectual property management are provided. The method includes defining a sequence of phases for an intellectual property management model. The phases are defined by task-based components in conjunction with a workflow component and a messaging component. The task-based components specify a sequence of tasks implemented for achieving a desired outcome for a respective phase and also specify at least one of a resource and a role assigned to implement one or more of the sequence of tasks. A portion of the task-based components interact and share information with others of the task-based components via the workflow component and messaging component, thereby integrating operations between respective task-based components and phases. The method also includes applying the intellectual property management model to a set of inputs associated with data corresponding to a request to protect a proposed idea or concept.

Abstract: A computer-implemented method, and computer program product, for switching the I/O protocol of a multiprotocol I/O adapter while a computer system including the multiprotocol I/O adapter is running. The method comprises running a multiprotocol I/O adapter using a first I/O protocol while a computer system including the multiprotocol I/O adapter is running, and logically removing the adapter from the system while the computer system continues running. The multiprotocol I/O adapter is then caused to switch to a second I/O protocol while the adapter is logically removed and the computer system continues running. While the computer system still continues to run, the multiprotocol I/O adapter is restarted. After restarting, the multiprotocol I/O adapter runs using the second I/O protocol while the computer system continues running. In a virtualization environment, the method allows a multiprotocol I/O adapter to meet the varying I/O requirements of one or more virtual machines.

Abstract: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: A data profile request is handles by utilizing data in a distributed file system. Tabular data is extracted from a data source and stored in a distributed file system. Each table in the tabular data is split by columns, which are each stored in separate files in a set of physical nodes of the distributed file system. In response to a data profiling request, a master node determines, based on the profiling request, which groups of files are needed to be on a same physical node in order to perform the profiling analysis. The master node creates jobs using physical nodes that contain the requisite files needed for each job.

Abstract: Systems and methods for reducing risk of service interruptions for one or more virtual machines (VMs) in a computing environment are provided. The method comprises computing a placement scheme for placing at least one VM on one or more hosts according to a set of placement constraints defined for the VM, wherein the set of placement constraints comprises at least one availability constraint defined for the VM, wherein the availability constraint designates a N resiliency level, wherein N corresponds to number of host failures that may occur before the services provided by the VM are interrupted.