Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

Abstract: Digital certificate public information is extracted using a processor from at least one digital certificate stored within at least one digital certificate storage repository. The extracted digital certificate public information is stored to at least one dynamically-created certificate public information directory. At least a portion of the digital certificate public information stored within the at least one dynamically-created certificate public information directory is provided in response to a digital certificate public information request.

Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

Abstract: Displays are generated on screens of computer interfaces that facilitate viewing search results in context. Each image returned as a search result is visually presented to a user with additional context images from the same digital media object from which the search result image is taken. If the media object is a slide presentation, the additional context images can include immediately preceding and succeeding slides or other slides in the presentation.

Abstract: Developing collective operations for a parallel computer that includes compute nodes includes: presenting, by a collective development tool, a graphical user interface (‘GUI’) to a collective developer; receiving, by the collective development tool from the collective developer through the GUI, a selection of one or more collective primitives; receiving, by the collective development tool from the collective developer through the GUI, a specification of a serial order of the collective primitives and a specification of input and output buffers for each collective primitive; and generating, by the collective development tool in dependence upon the selection of collective primitives, the serial order of the collective primitives, and the input and output buffers for each collective primitive, executable code that carries out the collective operation specified by the collective primitives.

Abstract: A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.

Abstract: A single array of pixels is used to obtain a plurality of different images at different levels of admitted exposure light from a common source level of exposure light. More particularly, first and second matrices of light-admitting elements are deployed in a single camera and disposed relative to focal lens light in front of corresponding first and second matrices of light-sensitive image sensors that are arrayed in a singular focal plane array in the camera and react equally to equal levels of color image information. The respective matrices of light-admitting elements transmit color image information from exposed focal lens light at different levels of brightness to their corresponding matrices of light-sensitive image sensors, wherein first and second images are acquired at the respective different levels of brightness from the respective matrices of the image sensors, and pixel data from the images combined to produce an HDR image.

Abstract: An apparatus for automating a prioritization of an incoming message, including a batch learning module that generates a global classifier based on training data that is input to the batch learning module. A feedback learning module that generates a user-specific classifier based on a plurality of feedback instances. A feature extraction module that receives the incoming message and a topic-based user model, infers a topic of the incoming message based on the topic-based user model, and computes a plurality of contextual features of the incoming message. A classification module that dynamically determines a priority classification strategy for assigning a priority level to the incoming message based on the plurality of contextual features of the incoming message and a weighted combination of the global classifier and the user-specific classifier, and classifies the incoming message based on the priority classification strategy.

Abstract: According to one embodiment of the present invention, a system analyzes data in response to detecting occurrence of an event, and includes a computer system including at least one processor. The system maps fields between the data and a fingerprint definition identifying relevant fields of the data to produce a fingerprint for the data. The data is deleted after occurrence of the event. The produced fingerprint is stored in a data repository, and retrieved in response to detection of the event occurrence after the data has been deleted. The system analyzes the retrieved fingerprint to evaluate an impact of the event on corresponding deleted data. Embodiments of the present invention further include a method and computer program product for analyzing data in response to detecting occurrence of an event in substantially the same manner described above.

Abstract: The invention is directed to increasing interoperability between web-based applications and hardware functions of a mobile device. The invention includes a thick-client hardware compatibility wrapper (HCW), which renders web-based applications and manages communication between hardware functionality and the web-based application. Specifically, the HCW monitors the web-based application and identifies commands to the hardware components of the mobile device. These commands are interpreted by the HCW, which then uses native calls to perform the hardware-specific activities. The HCW is also capable of calling functions on a webpage within the web-based application in response to query commands to the web-based application or in response to hardware events from the hardware components.

Abstract: A server may receive a first check-in corresponding to at least one person, wherein a check-in is a indication of presence. The server may receive a second check-in to form an aggregation of people. The server may characterize the aggregation based on the cumulative characteristics selected from at least one of the group consisting of age, marital status, and parental status associated with at least one of the first check-in and second check-in to form an aggregated population characteristic. The server may select at least one advertisement based on the aggregated population characteristic. The server may dispatch the at least one advertisement.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.

Abstract: A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate.

Abstract: A method for detecting and combating an attack in an industrial control system includes sending a command stream from a protection network of an industrial control system to at least one zone, the command stream comprising at least one command; concatenating the at least one command into at least one sequential command package comprising units or work; passing the at least one sequential command package to a crypto hash generator; generating at least one of unit of work hash codes or sequence hash codes; comparing the generated hash codes against a database of existing valid unit of work hash codes and sequence hash codes; and if a command stream fault is detected, generating an alert and accessing a database comprising emergency procedures.

Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

Abstract: Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

Abstract: According to one embodiment of the present invention, a system analyzes data in response to detecting occurrence of an event, and includes a computer system including at least one processor. The system maps fields between the data and a fingerprint definition identifying relevant fields of the data to produce a fingerprint for the data. The data is deleted after occurrence of the event. The produced fingerprint is stored in a data repository, and retrieved in response to detection of the event occurrence after the data has been deleted. The system analyzes the retrieved fingerprint to evaluate an impact of the event on corresponding deleted data. Embodiments of the present invention further include a method and computer program product for analyzing data in response to detecting occurrence of an event in substantially the same manner described above.

Abstract: A surface cleaning apparatus comprising a chamber, and a thermal transfer device. The chamber is capable of holding a semiconductor structure therein. The thermal transfer device is connected to the chamber. The thermal transfer device has a surface disposed inside the chamber for contacting the semiconducting structure and controlling a temperature of the semiconductor structure in contact with the surface. The thermal transfer device has a thermal control module connected to the surface for heating and cooling the surface to thermally cycle the surface. The thermal control module effects a substantially immediate thermal response of the surface when thermally recycling the surface.

Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.