Abstract: Metadata describing common Java classes is extracted and utilized to optimize a Java program's performance based on the code requirements of the application. Data mining techniques extract metadata and other information about different sets of JVM byte code written by multiple vendors to determine the design choices and optimizations made by each vendor in implementing their JVM. Then, byte code in a Java application being programmed is analyzed in comparison to each vendor's JVM metadata and information. Based upon the application's requirements (for example footprint, performance, etc.), recommendations are generated that yield a newly compiled rt.jar that combines the best practices of each vendor together or recommends a particular vendor's standard JVM that is best suited for the application.

Abstract: An apparatus for providing multi-directional signaling interface connection of a printed circuit card within a computer chassis. In one embodiment, a blind swap cartridge carries a circuit card that includes a first signaling interface connector in the form of a PCI edge connector. The edge connector is movable via a pivot point on the cartridge in a substantially transverse direction with respect to an insertion direction of said blind swap cartridge. In accordance with the present invention, a second signaling interface connector, such as a SCSI connector, is rigidly affixed to the exterior of the blind swap cartridge. The second signaling interface connector is preferably disposed on the cartridge in an orientation such that its connection direction is substantially aligned with the blind swap cartridge insertion direction. A flexible interconnect member is preferably utilized to couple the second signaling interface connector to the circuit card.

Abstract: A method and system that enables management software to quickly and efficiently access system specific information required for managing components/systems of a managed networked. Specifically, an automated process of generating the system definition and making the system definition available to system management software on a management server/system is provided as a component of the management software. A publicly available definitions database is provided that is readily available (and easily accessible) to the management server. The definitions database holds an updated list of definition files for all possible/designed component types that may be connected to the managed network. The management software executing on the management server/system is enhanced to include a utility that accesses a public (external) definitions database when required during a setup/registration of a managed component.

Abstract: A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.

Abstract: A lightweight, low cost solution provides inter process communications (IPC) in a network processing environment. A method of inter process communication (IPC) between General Purpose Processors in a network processing environment uses software based functions (Application Program Interfaces (APIs)) that enable inter process communication between processors in a network processing environment. The software enabled functions open and close inter process communication paths for transmitting and receiving of inter process communication frames and allow the inter process communication frames to be transmitted to one or several processors in said network processing environment. The software has the capability of selecting either data or control path in said network processing environment to transmit or receive said inter process communication frames.

Abstract: A system and method is provided for real time transcription or translation services. In one aspect of the system and method, a user requests transcription/translation service with certain service parameters. It is determined what resources can be used for such service, and, if all the service parameters can be met, the service is performed. Resources include live stenographers or translators, and computer processing power. If all the service parameters can not be met, it is determined whether to perform the service by meeting only some of the service parameters. These determinations may be programmed into the system beforehand. In another aspect of the system and method, a user makes a request for transcription/translation service, and the request is displayed so that stenographers or translators may make bids to perform the transcription/translation service. In some embodiments, the request is only displayed to those stenographers or translators who are determined to be able to perform the service.

Abstract: A method and apparatus for data transmission transmits both compressed and noncompressed data over each of a plurality of transmission paths. A data identification pattern is used to request a type of data from a memory having a plurality of data types stored within it. A handshaking control module is provided to select the correct type of data from the memory and place it on the output of the memory. The requested data type is then transmitted to a data decompression module via an interface. The data transmission can occur on any one of a plurality of data transmission paths when the data being transmitted is either Linework or Linework control data. When the data decompression module receives the data, it is then routed to any one of a plurality of data decompression systems based upon the results of the evaluation of the data identification pattern. The routing of the received data is wholly dependent upon the data identification pattern and independent of which transmission path the data was received on.

Abstract: A method and system for allowing a server blade in a blade chassis to use a remote universal serial bus (USB) device. Multiple USB devices are coupled to a management module in the blade chassis. A persona describing only authorized USB devices is sent to a reconfigurable input/output (I/O) device in the server blade in the blade chassis, allowing the server blade to utilize the remote USB device(s).

Abstract: A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Abstract: A chip sandwich includes a heat sink, a retention module, a computer chip mounted in a socket on a mother board, a wave washer spring and a mounting plate. The heat sink is mounted on the retention module using cams, hooks and heat sink tabs to provide an initial orientation of the heat sink over the computer chip. To provide final contact pressure between the heat sink and the computer chip, a wave washer spring oriented beneath the computer chip and under the mother board provides an upward pressure against the bottom of the mother board, and particularly against the center of the computer chip. Thus, by the wave washer spring pushing against the center of the computer chip, secure contact pressure is provided between the heat sink and the computer chip, while minimizing the amount of pressure between the computer chip's pins and the chip socket.

Abstract: A retention module firmly secures a heat sink for a computer chip. The retention module is oriented about the computer chip on a circuit board. The retention module has a rotatable wire form that has two loops. When the rotatable wire form is rotated, the two loops press against an impingement shelf on the heat sink, forcing the heat sink against the retention module and the computer chip. The two loops are angularly offset to each other, thus compensating for torsion lag between the two loops when the two loops are pressed against the impingement shelf.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: An unintended recipient initiates a reply to the sender and all other recipients of an original email. The reply contains a “hot button” feature in the email client application to enable the email client application of the recipient of the reply to auto designate the unintended recipient in the recipient of the reply's address book. When the recipient of the reply's email client application creates a future email, it is determined if the recipient of the future email has been designated as a potential unintended email recipient. If so, the email client generates a notification that the future email recipient potentially is an unintended recipient of the future email. The designation enables notification means for avoidance of initiating future erroneous emails addressed to an unintended recipient.

Abstract: A nanoprobe includes a substrate having a layer, which forms a projected portion. A plurality of conductive lines is adhered to the projected portion and the lines extend beyond an end of the projected portion by a distance to form contact points, wherein the lines are connected to material of the projected portion to provide stiffness and the contact points provide flexibility during use.

Abstract: In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.

Abstract: A portable fax machine includes a pen-based input device, having a writing pen and a writing pad, enabling a user to write documents for fax transmission on the writing pad by means of the writing pen. The input device is capable of generating data representative of the moving trace of the writing pen. An encoder transfers the data representative of the moving trace of the writing pen into fax data format. A dialer inputs the fax number of a destination to set up a connection. A fax transmission device transmits to the destination the data in the fax data format output by the encoder.

Abstract: A method and system for accessing a remote real communication port (“COM port”) from a server blade in a server blade chassis by creating a virtual COM port in the server blade. A basic input/output system (BIOS) controller monitors an internal COM port in the server blade for communication traffic. Upon detecting the communication traffic, the BIOS controller reroutes the traffic to a virtual USB COM port created by the BIOS controller chipset. The virtual USB COM port directs the communication traffic to an internal universal serial bus (USB) device in the server blade. The USB device then forwards the traffic to an Ethernet media access controller (MAC) input/output (I/O) on a sideband channel to a remote system, which passes the communication traffic to a real COM port in the remote system.

Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

Abstract: To provide an information retrieval system, a method for information retrieval, a program for executing the information retrieval, and a storage medium comprising the program for executing the information retrieval The information retrieval system according to the present invention comprises: means for generating and storing a predetermined type matrix from said document-attribute matrix, means for generating said document-attribute submatrix from documents being added to said database during a specific time period, means for updating said predetermined type matrix using knowledge with respect to said document-attribute submatrix and for executing the singular value decomposition on updated said predetermined type matrix to execute dimension reduction of all document-attribute matrices stored within said database, and means for retrieving information with respect to a user input query using said dimension reduced document-attribute matrix.

Abstract: A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.