Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser (VCSEL) diode. The VCSEL diode is biased by a bias supply. The integrated loop inductor may be integrated in CMOS technology and on the same IC chip as either/both of the FET driver and the VCSEL diode. The photodetector is in a semiconductor (silicon) layer that may be on an insulator layer, i.e., SOI. One or more ultrathin metal electrodes (<2000 ?) on the silicon layer forms a Schottky barrier diode junction which in turn forms a quantum well containing a two dimensional electron gas between the ultrathin metal electrode and the Schottky barrier diode junction.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: An apparatus, system, and method are disclosed for integrating the steps of securing and aligning a ramp to the pallet. A pallet mounting bracket secures to a pallet and mates with a corresponding ramp mounting bracket secured to a ramp. A pallet mounting bracket includes a registration receptacle that receives a registration member secured to the ramp mounting bracket in order to position the ramp with respect to the pallet. A driving member secured to the pallet mounting bracket engages a corresponding engagement portion on the ramp mounting bracket as the ramp is lowered into place next to the pallet. The driving member urges the engagement portion toward the pallet thereby urging a fastener secured to the ramp mounting bracket into engagement with a locking portion secured to the pallet mounting bracket thereby locking the ramp into position in alignment with the pallet.

Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract: A mechanism to build public file packages across multiple hosts and platforms is provided. A file package is created and builder processes (or simply “builders”) distributed among the hosts build a file set into the package. The builder may be represented by an executable file deployed on the host that may be, but is not necessarily, the target of the file set. A set of builders may be associated with a particular file package and invalid builders may be precluded from “working” on the package. A build event may be associated with the build and triggered when all builders have completed their respective builds.