Abstract: An embodiment establishes a transmission performance database that comprises performance data related to transmission of data across a plurality of data channels of a network. The embodiment defines an initial data chunk size for a first data object transmitted across a first data channel of the plurality data channels of the network. The embodiment transmits the first data object across the first data channel according to the initial data chunk size. The embodiment collects performance data for the first data channel. The embodiment evaluates transmission performance of the first data channel based at least in part on the performance data of the first data channel. The embodiment generates a recommendation to adjust the initial data chunk size of the first data object based on the transmission performance of the first data channel. The embodiment adjusts the initial data chunk size based at least in part on the recommendation.

Abstract: A method, apparatus and computer program product for homomorphic computation enables secure computation of determinants of a matrix under Fully Homomorphic Encryption (FHE). According to this disclosure, encrypted data that contains the values of a matrix is received at a server. The matrix is separated into at least a first portion, and a second portion. Each portion is configured as a square. A first data vector of ciphertext is computed for the first portion, and a second data vector of ciphertext is computed for the second portion. Under FHE, determinants of the first and second data vectors are computed as Single Instruction Multiple Data (SIMD) operations to generate a set of results. The set of results are then used to compute a determinant of the matrix. The determinant may then be used for FHE-based analytics.

Abstract: Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

Abstract: A computer implemented method processes alerts. A computer system creates a representation of an alert received for processing. The computer system determines a similarity of the alert with previously processed alerts using the representation of the alert and representations of the previously processed alerts. A first evaluator in the computer system evaluates an alert level for the alert based on previously processed similar alerts in response to the similarity being above a similarity threshold for similar alerts. A second evaluator in the computer system evaluates, the alert level for the alert using a machine learning model in response to the similarity not being above the similarity threshold.

Abstract: A crystallization seed layer in a substrate, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the crystallization seed layer, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A plurality of memory structures configured in a crossbar array, each including a crystallization seed layer, a phase change material layer above, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A method including forming a crystallization seed layer, forming a phase change material layer, forming a top electrode and a bottom electrode on the substrate, each adjacent to a vertical side surface of the phase change material layer.

Abstract: Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Abstract: Embodiments of the present invention are directed to a two-layer adhesive and methods of using the same to secure an electronic device to an organism. In a non-limiting embodiment of the invention, a surface of the organism is coated with a first adhesive layer (bottom layer). The first adhesive layer is cured and a surface of the cured first adhesive layer is coated with a second adhesive layer (top layer). An electronic device is positioned on the second adhesive layer prior to curing the second adhesive layer. The second adhesive layer is then cured, thereby embedding the electronic device within the second adhesive layer. The bottom layer and the top layer are selected such that the bottom layer releases upon exposure to a first solvent after a first duration and the top layer releases upon exposure to a second solvent after a second duration more than the first duration.

Abstract: A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor.

Abstract: In an approach to automated social distancing recommendations, one or more computer processors monitor first data associated with a utilization of a physical space. One or more computer processors determine the first data associated with the utilization of the physical space exceeds a space utilization threshold. Based on the first data associated with the utilization of the physical space exceeding the space utilization threshold, one or more computer processors generate second data associated with the physical space. One or more computer processors send a notification, where the notification includes the generated second data associated with the physical space.

Abstract: Embodiments of the invention are directed to a computer-implemented method that includes accessing, using a processor system, a three-dimensional (3D) model of a device-under-design (DUD). The processor system is used to receive a first design operation associated with the 3D model of the DUD. A collaboration dependency model is used to make a prediction of a dependency relationship between the first design operation and a second design operation.

Abstract: Computer-implemented methods for optimizing memory access for systems with memory expanders are provided. Aspects include analyzing a source code of a program to identify each data structure that will be accessed by the program during execution of the program, determining a predicted access pattern for each data structure, and determining a type of each data structure. Aspects also include calculating a data access score for each data structure based at least in part on the predicted access pattern and the type and creating an executable code of the program based on the source code. The executable code includes a memory allocation value for each data structure that is determined based on the data access score for each data structure.

Abstract: According to one embodiment, a method, computer system, and computer program product for adjusting an audible area of an avatar's voice is provided. The present invention may include receiving, at a microphone, a source audio; creating a received audio; calculating, by a generative model, a voice propagation distance of a user based on the source audio, the received audio, and a templated text sentence describing a category of a mixed reality environment experienced by the user; drawing a virtual circle within the mixed reality environment centered on a user avatar representing the user and with a radius equal to the voice propagation distance; and transmitting the source audio to one or more participants within the mixed-reality environment represented by one or more participant avatars located within the virtual circle.

Abstract: Embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. A non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. A set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. A comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. A compatibility testing recommendation is generated based at least in part on a result of the comparison.

Abstract: A method, a computer program product, and a computer system fuse features for multi-modal classifications for a plurality of modality inputs. The method includes receiving a request indicative of the modality inputs to be selected. The method includes performing an embeddings level fusion operation to concatenate features from the modality inputs. The method includes performing a multi-modal discriminative feature level fusion operation that integrates feature representations learned by applying different network structures on the modality inputs. The method includes determining weights of the concatenated features and the feature representations based on a measure of the concatenated features and the feature representations indicative of affecting a final prediction performance. The method includes generating fused features for the modality inputs based on the concatenated features, the feature representations, and the weights.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: Embodiments of the invention are directed to a computer-implemented method. A non-limiting example of the computer-implemented method includes accessing, using an explanation generator module of a processor system, information of a recommendation associated with an application, information of the application, and information of a user of the application. The explanation generator module of the processor system is used to determine an explanation format of an explanation of the recommendation based at least in part on the information of the recommendation associated with the application, the information of the application, and the information of the user of the application.

Abstract: A method, computer program product, and computer system are provided for testing drives in a redundant array of independent disks (RAID) array. The method includes: mirroring data from a selected drive to be tested in a RAID array to spare storage space in the RAID array; and, once the data is successfully mirrored, testing the selected drive to identify a preemptive failure of the selected drive. The RAID may be a traditional RAID (TRAID) array and the spare space may be a spare physical drive independent of array drive members. The RAID array may alternatively be a distributed RAID (DRAID) array and the spare space may be spare capacity spread through the array drive members.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate feed-forward design of three-dimensional quantum chips are provided. According to an embodiment, a system can comprise a processor that executed computer executable components stored in memory. The computer executable components can comprise an analysis component that performs an analysis of a first layout of a first quantum chip. The computer executable components further comprise a modification component that modifies a second layout of a second quantum chip based on the analysis of the first layout.

Abstract: Devices and/or computer-implemented methods to facilitate a multipole filter on a quantum device with multiplexing capability and signal separation to mitigate crosstalk are provided. According to an embodiment, a device can comprise an interposer substrate comprising a readout resonator. The device can further comprise a qubit chip substrate comprising a qubit coupled to the readout resonator and to a multipole filter.

Abstract: An approach for optimizing security token exchange. The approach receives a first request from a client. The approach extracts a first security token and an API reference. The approach validates the first security token. If the security token is valid, then the approach, calls the API and retrieves a second security token, embeds the second security token in the API and sends a second request with a third security token and the reference to the API to another application in a different domain.