Abstract: In an approach to improving the predictive accuracy of classifiers, one or more computer processors calculate one or more training set statistics. The one or more computer processors generate one or more balanced training sets based on one or more calculated training set statistics. The one or more computer processors train one or more cognitive models utilizing one or more unbalanced training sets and one or more generated balanced training sets. The one or more computer processors determine a fitness of the one or more trained cognitive models. The one or more computer processors adjust one or more training sets based on the determined fitness of the one or more cognitive models.

Abstract: An adhesive composition includes a photoinitiator and an acrylate-cyanoacrylate monomer. The acrylate-cyanoacrylate monomer includes at least one acrylate functional group to enable photo-curing of the adhesive composition and at least one cyanoacrylate functional group to enable latent curing of the adhesive composition.

Abstract: Development of computer programs is facilitated. An interface of a program is created and that program interface encapsulates an existing spreadsheet, such that the spreadsheet itself is the calculation engine of the program. The logic of the spreadsheet is not re-coded, and the spreadsheet is hidden from and unchangeable by the user. The interface provides exclusive input and output access to the spreadsheet.

Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Abstract: A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups. The physical data group includes a plurality of bits and each subgroup includes a subplurality of bits. The output shuffler performs an output shuffle sequence for providing a predefined output pattern of ordered subplurality data bits. The predefined output pattern of ordered subplurality data bits is applied to the input shuffler. The input shuffler performs a reverse shuffle sequence. For each shuffle transfer a number of first header bytes of a packet are located at a first one of a plurality of physical layer links. Both the output shuffler and the input shuffler are implemented with minimized logic required to keep a largest multiplexer as a 4-to-1 multiplexer, resulting in minimal area and power being used for implementing the shuffle sequence and reverse shuffle sequence.

Abstract: A method for process modeling includes reading a record of executions of a process including at least first and second activities, and identifying in one of the executions in the record respective first and second lifespans of the first and second activities, defined by respective initiating and finish events, such that the initiating event of the second lifespan occurs during the first lifespan. A graphic model of the process is generated, so as to reflect a concurrency of the first and second activities, responsively to occurrence of the initiating event of the second lifespan during the first lifespan.

Abstract: The present system and associated method resolve the problem of providing statistical performance guarantees for applications generating streams of read/write accesses (I/Os) on a shared, potentially distributed storage system of finite resources, by initiating throttling whenever an I/O stream is receiving insufficient resources. The severity of throttling is determined in a dynamic, adaptive way at the storage subsystem level. Global, real-time knowledge about I/O streams is used to apply controls to guarantee quality of service to all I/O streams, providing dynamic control rather than reservation of bandwidth or other resources when an I/O stream is created that will always be applied to that I/O stream. The present system throttles at control points to distribute resources that are not co-located with the control point.

Abstract: A system, apparatus and method of displaying a Web page accessed via a link are provided. The system, apparatus and method display the Web page by determining whether an opened browser session is locked. If the opened browser session is locked a new browser session is opened to display the Web page. Otherwise, the Web page is displayed in the opened browser session if it is so configured.

Abstract: A method, apparatus, and computer instructions for authorizing execution of an application on the data processing system. A request is received to execute the application, wherein the request originates from a remote data processing system and wherein the request includes a digital certificate and the application. The digital certificate is verified in response to receiving the request. Responsive to verifying the digital certificate, a digital digest is calculated for the application to form a calculated digital digest. The calculated digital digest is compared with a set of digital digests from a trusted source. The application is executed if a match between the calculated digital digest and set of digital digests occurs.

Abstract: A method, apparatus, and computer instructions for obtaining a logical unit. A request is sent for the logical unit. In the depicted examples, the request is sent to a multicast IP address. Responses to the request for the logical unit are received from a number of responders. A responder is identified from the set of responders to form a selected responder. The selected responder is identified based on at least one connection metric between the data processing system and the set of responders. The logical unit is retrieved from the selected responder.

Abstract: When a blade and/or interconnect device is inserted into the chassis of a powered or live server the procedure is known as hot-plugging. Before power is applied to the hot-plugged blade and/or interconnect device the fabric type of already installed blades and/or interconnect devices is correlated with fabric types of newly hot-plugged blade and/or interconnect device. Depending upon results of the correlation, power to the hot-plugged blade and/or interconnect device is allowed or denied.

Abstract: An automated way to detect differences in the values of program variables/expressions and the order of execution between one run and another. A collection mode saves the values of expressions/variables at collection points in the program. On a subsequent execution during the detection mode, these saved values of the same expressions/variables are recalled and compared with the current values. Advantageously, the user selects the collection points within the program at which variable information can be gathered and compared; and these collection points may include: breakpoints set by a debugging program or by the user; collection points set by the user, and entry and/or exit points and/or points within program structures, such as procedure calls, control blocks, etc. Setup of the collection mode includes the capability to modify the expressions/variables, the tolerance or the acceptable alternatives, and the position and number of collection points.

Abstract: There is provided a memory system on a chip. The memory system includes a configurable memory having a first mode of operation wherein the configurable memory is configured as a cache and a second mode of operation wherein the configurable memory is configured as a local, non-cache memory. A selection of any of the first mode of operation and the second mode of operation is capable of being overridden by an other selection of an other of the first mode of operation and the second mode of operation. The configurable memory may be configured at manufacture time, at burn-in time, and/or during program execution. Moreover, an access mode of the configurable memory may be determined from an address corresponding to a memory access instruction.

Abstract: Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.

Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

Abstract: A method, apparatus, and computer implemented instructions for setting a time out value. A path is identified from a set of paths from the data processing system to a destination to form an identified path, wherein the identified path has a largest latency in the set of paths. The data is routed to the destination using the identified path. The latency is measured for the data sent on the identified path to form a measured latency. The time out value is set using the measured latency, wherein the time out value is used to initiate a computer implemented process.

Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.

Abstract: The invention discloses a method capable of writing/erasing high-density data, preferably on a phase-change recording media. A preferred embodiment of the invention features a novel thermal near-field heater that may be employed in an assembly enabled by the present method. The method may be preferably used for writing in a substantially thermal near-field mode. The invention provides advantages of writing densities greater than that of diffraction limited systems, for example, writing densities of approximately greater than 100 Gbit/ inch2, and writing speeds approximately greater than 100MHz.

Abstract: An improved method and system is described for implementing double dispatch extensibly and efficiently in single-dispatch object-oriented programming languages. Objects of type Visitor encapsulate double dispatch functionality, while objects of type Element act as operands. Double dispatch takes place by calling Accept on an object of type Element, passing an object of type Visitor as an argument. Concrete classes of type Element are added in groups, each group deriving from an abstract subclass of Element. An AbstractElement class augments the Element interface with an Accept operation that takes an object of type AppVisitor as an argument, where AppVisitor is an abstract subclass of Visitor. AppVisitor overrides the base class Visit operation to test the type of its Element argument, casting it into an AppElement and calling its augmented Accept.

Abstract: A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.