Abstract: A method, apparatus, and computer instructions for authorizing execution of an application on the data processing system. A request is received to execute the application, wherein the request originates from a remote data processing system and wherein the request includes a digital certificate and the application. The digital certificate is verified in response to receiving the request. Responsive to verifying the digital certificate, a digital digest is calculated for the application to form a calculated digital digest. The calculated digital digest is compared with a set of digital digests from a trusted source. The application is executed if a match between the calculated digital digest and set of digital digests occurs.

Abstract: When a blade and/or interconnect device is inserted into the chassis of a powered or live server the procedure is known as hot-plugging. Before power is applied to the hot-plugged blade and/or interconnect device the fabric type of already installed blades and/or interconnect devices is correlated with fabric types of newly hot-plugged blade and/or interconnect device. Depending upon results of the correlation, power to the hot-plugged blade and/or interconnect device is allowed or denied.

Abstract: An automated way to detect differences in the values of program variables/expressions and the order of execution between one run and another. A collection mode saves the values of expressions/variables at collection points in the program. On a subsequent execution during the detection mode, these saved values of the same expressions/variables are recalled and compared with the current values. Advantageously, the user selects the collection points within the program at which variable information can be gathered and compared; and these collection points may include: breakpoints set by a debugging program or by the user; collection points set by the user, and entry and/or exit points and/or points within program structures, such as procedure calls, control blocks, etc. Setup of the collection mode includes the capability to modify the expressions/variables, the tolerance or the acceptable alternatives, and the position and number of collection points.

Abstract: There is provided a memory system on a chip. The memory system includes a configurable memory having a first mode of operation wherein the configurable memory is configured as a cache and a second mode of operation wherein the configurable memory is configured as a local, non-cache memory. A selection of any of the first mode of operation and the second mode of operation is capable of being overridden by an other selection of an other of the first mode of operation and the second mode of operation. The configurable memory may be configured at manufacture time, at burn-in time, and/or during program execution. Moreover, an access mode of the configurable memory may be determined from an address corresponding to a memory access instruction.

Abstract: Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.

Abstract: A system and method for implementing distributed transactions using configuration data that is available to all applications which may wish to access the data. Added to the configuration data is at least one status indicator to allow applications to ascertain the status of updates without performing a database-specific distributed transaction. An application which is preparing to write/update stored information must first change the at least one status indicator associated with the underlying storage. Thereafter, any other application which has a need to read or write the stored information will readily ascertain the status of the stored information from the configuration data. The other application which has need of the data may choose to read the old and/or partially updated data or may wait until the update has been completed and the at least one status indicator has been changed to indicate completion of the update.

Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

Abstract: A linear actuator incorporates a DC motor whose stator is secured to a frame. A shaft is coupled to the rotor of the DC motor one end of which is circumferentially coupled to the inside of a torsion spring and the outer section of the torsion spring is coupled to the frame. The center section of the shaft is circumferentially raised creating first and second shaft stops. The middle of the shaft is threaded and threadedly coupled to a translating actuator which has a radial raised portion which engages a section of the frame. The radial raised section provides a radial stop and prevents the translating actuator from rotating. Additional radial raised portions on the translating actuator create first and second stops that engage the first and second shaft stops at each extreme of travel. The first stop keeps the threads from binding in a retracted position and the second stop keeps the threads from binding in the extended position.

Abstract: A method, apparatus, and computer implemented instructions for setting a time out value. A path is identified from a set of paths from the data processing system to a destination to form an identified path, wherein the identified path has a largest latency in the set of paths. The data is routed to the destination using the identified path. The latency is measured for the data sent on the identified path to form a measured latency. The time out value is set using the measured latency, wherein the time out value is used to initiate a computer implemented process.

Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.

Abstract: The invention discloses a method capable of writing/erasing high-density data, preferably on a phase-change recording media. A preferred embodiment of the invention features a novel thermal near-field heater that may be employed in an assembly enabled by the present method. The method may be preferably used for writing in a substantially thermal near-field mode. The invention provides advantages of writing densities greater than that of diffraction limited systems, for example, writing densities of approximately greater than 100 Gbit/ inch2, and writing speeds approximately greater than 100MHz.

Abstract: The objective of the present invention is the efficient analyzation of the structure of an array.

Abstract: A method and system for evaluating the serviceability of a system is disclosed. The method and system include obtaining a comparison of the system with a plurality of criteria and calculating at least one serviceability score based on the comparison. The comparison includes an objective measure of the serviceability of the system for each of the plurality of criteria.

Abstract: An improved method and system is described for implementing double dispatch extensibly and efficiently in single-dispatch object-oriented programming languages. Objects of type Visitor encapsulate double dispatch functionality, while objects of type Element act as operands. Double dispatch takes place by calling Accept on an object of type Element, passing an object of type Visitor as an argument. Concrete classes of type Element are added in groups, each group deriving from an abstract subclass of Element. An AbstractElement class augments the Element interface with an Accept operation that takes an object of type AppVisitor as an argument, where AppVisitor is an abstract subclass of Visitor. AppVisitor overrides the base class Visit operation to test the type of its Element argument, casting it into an AppElement and calling its augmented Accept.

Abstract: A method and system for automatically determining the location of equipment mounted in a rack is disclosed. The method and system comprises providing a plurality of signal emitting elements within the rack and transmitting positional information from the rack to the equipment via at least one signal emitting element of the plurality of signal emitting elements. The equipment receives the positional information transmitted by the at least one signal emitting element, and is capable of reporting the positional information, such that the location of the equipment can be determined.

Abstract: According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

Abstract: A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

Abstract: Method for providing at least a portion of a disguised password in an undisguised form is described. More particularly, a program is described having a capability of displaying a single character at a time, more than one character at a time or all of otherwise disguised characters of a password in an undisguised form in response to a successful pre-password check.

Abstract: Prior methods of encryption of the token or “cookie” communicated to a client by a server use a symmetric method of encryption which does not permit the client to look at the state information. The present invention permits the client to view the state information, but not modify it, by using an asymmetric encryption method.

Abstract: Method and apparatus to enable measurement of response times, for example at one-second resolution or better, in a system where a starting location and ending location of processing are different. A timing data that signals a start of data processing is entered into a logging device and recorded in a system log file with a time stamp placed according to a system clock of the logging device. Output data from a CIS interface or TV interface that signals the end of processing is sent to the logging device and recorded in the system log file 20 with a time stamp placed according to the system clock of the logging device. The processing time is calculated with reference to the time stamps in the log data in the system log file associated with the processing.