Abstract: The invention generally relates to the utilization of electric power, and more particularly to systems and methods for selectively utilizing secondary power sources during peak power times. A method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.

Abstract: A method to provide a signal using a communication link. The method disposes a passive transponder on the communication link, where that passive transponder includes a memory. The method reads information relating to the communication link from the memory, and then, based upon that information, adjusts certain characteristics of a signal provided using the communication link.

Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

Abstract: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of quest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.

Abstract: A system is provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance.

Abstract: Systems and methods are provided for dynamically controlling application placement and server resource allocation in a distributed system wherein a performance manager and power manager collaborate during run-time execution of data processing tasks to coordinate management and control of workload placement and server usage and dynamically determine a tradeoff between performance level and power usage that meets power and performance objectives.

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract: A method (100) and a system (300) for applying digital signatures (206, 216, and 222) to translated content (and other content) can include a presentation (309) and a user interface presented on the presentation device. The system can further include at least one processor (307) that operates to create (102) the user interface in a first language as part of an application, enables (104) the entering of data into the user interface and the digital signing of the data by a first user, translates (106) the user interface to at least a second language, and presents (108) the data to at least a second user using the application. A recipient device can verify (110) the digital signatures where a verification of the digital signatures independently verifies a data signature (222), a user interface signature (206), and a translated user interface signature (216).

Abstract: A plurality of user defined schedules are received for collecting data on a plurality of resources. A schedule is generated for data collection on at least one resource, based on processing the plurality of user defined schedules to eliminate redundant data collection on the at least one resource. Operations are executed on the at least one resource in accordance with the generated schedule.

Abstract: Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level.

Abstract: A method, computer program product, and system for determining a number of users corresponding to a server load including simulating one or more virtual users on a test computer system on coupled to network. One or more client requests are sent from each of the one or more virtual users to a server application executed on a server computer system coupled to the network. A metric indicative of a load on the server computer system is measured. The metric is compared to a predetermined value; and the number of the one or more virtual users is changed based on the difference between the metric and the predetermined value until the metric is within a predetermined range of the predetermined value.

Abstract: A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.

Abstract: A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

Abstract: Multiple application threads write to the same file in parallel. The file is written to on a file cluster-by-file cluster basis. For each file cluster of a number of file clusters of the file, a block of a memory cluster is allocated to an application thread, where the memory cluster corresponds to the file cluster, and the block is written to by the application thread until the block is finished, until all the blocks of the memory cluster are finished. A block may be finished where the application thread has completely written to the block, or the application thread has no further data to write to the block. Thereafter, the memory cluster is registered within a queue, from which it is read by a file writer thread, which writes the memory cluster to the file cluster. Each application thread that is to write to the file performs this process.

Abstract: A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.

Abstract: The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

Abstract: The present invention utilizes the main Java package (javax.jcr.binary) for saving the node property path and other relevant retrieving information within the serialized XML node files so that the intended large binary data remains inside the content repository while the corresponding node is being serialized. A data centric application which requires processing of the serialized XML node file can then deal with a much reduced sized XML file. This can improve the performance greatly in terms of memory usage and processing speed for XML processors such as DOM. During the consuming phase of the data centric applications, the binary data property is streamed from its source JCR repository into the target repository by looking up its original property path and other retrieving information.