Patents Assigned to International Business Machines Corporaton
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Patent number: 7080298Abstract: A method for testing an electronic circuit includes selecting an input signal using a first multiplexer, selecting a signal to be input to the first multiplexer using at least one other multiplexer, and controlling the at least one other multiplexer using a selection signal output from a control circuit.Type: GrantFiled: February 4, 2003Date of Patent: July 18, 2006Assignees: Toshiba America Electronic Components, International Business Machines CorporatonInventors: Naoki Kiryu, Louis B Bushard
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Patent number: 7007171Abstract: A method and apparatus for forming a security enclosure having improved fold retention. In particular, the enclosure is formed by folding a flexible tamper respondent cloth around an electronic assembly. An adhesive on the inner folded surfaces of the cloth temporarily retains the folds. The enclosure is then exposed to heat and pressure to promote improved adhesion strength of the adhesive, thereby improving fold retention.Type: GrantFiled: September 1, 2000Date of Patent: February 28, 2006Assignee: International Business Machines CorporatonInventors: Giuseppe Butturini, Mario L. Cesana, Donald S. Farquhar, Fulvio Fontana
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Patent number: 6944300Abstract: A method for migrating a base chip key from a first computer system to a second computer system is disclosed. A first computer system includes a base chip key 1, and a second computer system includes a base chip key 2. Using a first certificate for the base chip key 1, a manufacturer of the second computer system generates a second certificate for the base chip key 1. Similarly, using a first certificate for the base chip key 2, a manufacturer of the first computer system generates a second certificate for the base chip key 2. A first data packet is then sent from the first computer system to the second computer system. The first data packet includes a first random number and all the data required to reproduce the base chip key 1 in the first computer system. The first data packet is also encrypted with the base chip key 1's public key.Type: GrantFiled: June 22, 2001Date of Patent: September 13, 2005Assignee: International Business Machines CorporatonInventors: David Carroll Challener, Hernando Ovies
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Publication number: 20050082531Abstract: A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATONInventor: Kern Rim
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Publication number: 20050078605Abstract: Messages arriving at a receiver are managed to ensure proper ordering of the messages. To facilitate proper ordering, a message sequence number is used, as well as matching criteria to match a correctly sequenced message with a posted receive. In response to processing a message, a check is made as to whether previously out of order messages can now be processed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Applicant: International Business Machines CorporatonInventors: Su-Hsuan Huang, William Tuel
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Publication number: 20040268335Abstract: Instructions of a loop are related in instruction chains represented by a data dependency graph with multiple first nodes for the instruction chains (either in a backward or forward direction). These instructions are modulo scheduled for execution by a processor. Execution parameters for each instruction denote execution relationships with previous instructions including latencies from execution of previous instructions and processor resources used by the instruction for execution. The instructions are ordered for scheduling according to a priority value for each instruction, which may be determined in a number of ways. Ordering starts with all instructions that have the highest priority value. Ordering continues with instructions related to instructions that have already been ordered; those instructions that are related and have a given priority value for the unordered instructions. After all instructions have been ordered they are modulo scheduled.Type: ApplicationFiled: November 6, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATONInventors: Allan Russell Martin, James Lawrence Mcinnes
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Publication number: 20040133690Abstract: A single firewall or cluster of firewalls with a public IP address is interfaced to an internet public subnet to receive service requests for a cluster of network servers. A first private subnet with a plurality of private IP addresses is interfaced to the single firewall or cluster of firewalls to receive the service requests after passing through a firewall. A plurality of redundant load balancers with a respective plurality of private IP addresses are interfaced to the first private subnet to receive the service requests after passing through the first private subnet. The load balancers are interfaced to a second private subnet. The network servers with respective private IP addresses are interfaced to the second private subnet to receive the service requests from the load balancers. At an initialization time, a private IP address is defined for the network load balancer system within the internet access subnet.Type: ApplicationFiled: September 30, 2003Publication date: July 8, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATONInventors: Pascal Chauffour, Eric Lebrun, Valerie Mahe
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Publication number: 20040095390Abstract: The invention relates to a method of performing a drag-and-drop operation of an object onto a container of a set of containers, the method comprising the steps of:Type: ApplicationFiled: November 6, 2003Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATONInventors: Andreas Arning, Frank Leymann, Dieter Roller, Roland Seiffert
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Publication number: 20030115064Abstract: The present invention comprises receiving speech input from two or more speakers, including a first speaker (such as a customer service representative for example); blocking a portion of the speech input that originates from the first speaker; and processing the remaining portion of the speech input with a computer. The blocking and processing are real-time processes, completed during a conversation. One example is a method for de-cluttering speech input for better automatic processing, by removing all but the pertinent words spoken by a customer. Another example is a system for executing methods of the present invention. A third example is a set of instructions on a computer-usable medium, or resident in a computer system, for executing methods of the present invention.Type: ApplicationFiled: December 17, 2001Publication date: June 19, 2003Applicant: International Business Machines CorporatonInventors: Carl Phillip Gusler, Rick Allen Hamilton, Timothy Moffett Waters
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Publication number: 20020120898Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.Type: ApplicationFiled: February 28, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporatonInventors: Howard H. Chen, Li-Kong Wang, Louis L. Hsu, Sang H. Dhong, Tin-chee Lo
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Patent number: 6343309Abstract: A method and apparatus for processing hierarchical graphics data from an application. The data processing system includes a plurality of threads in which a first thread receives graphics data from the application. The data stream is partitioned into workgroups and a sequence number is associated with each workgroup identifying the order in which the workgroup should be processed. Each thread processes a unique portion of the workgroups. Processed workgroups are stored in a memory associated with the thread processing that workgroup. The primary thread dispatches the processed workgroups from each of the memories associated with the threads to a rasterizer for the graphics display device. The workgroups are dispatched in an order indicated by the sequence number associated with each processed workgroup.Type: GrantFiled: September 30, 1996Date of Patent: January 29, 2002Assignee: International Business Machines CorporatonInventors: Paul A. Clarke, Brian Horton
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Patent number: 5719070Abstract: A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.Type: GrantFiled: October 2, 1996Date of Patent: February 17, 1998Assignee: International Business Machines CorporatonInventors: Herbert Carl Cook, Paul Alden Farrar, Sr., Robert Michael Geffken, William Thomas Motsiff, Adolf Ernest Wirsing
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Patent number: 5561568Abstract: To achieve fast positioning of a head by determining an initial value dynamically from state variables of a system at a switching time of control modes. In a recording device having a head, a recording media including a plurality of tracks accessed by the head, and a motor for moving the head, in order to position the head to a target track by switching control modes and outputting a control signal value u(n) to drive the motor in response to an input signal value y(n) representing a difference between a current position of the head and the target track, the gain of a control system having the input and control signal values as state variables is changed only at a mode switching time.Type: GrantFiled: October 16, 1992Date of Patent: October 1, 1996Assignee: International Business Machines CorporatonInventor: Masashi Kisaka
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Patent number: 5138506Abstract: A lubricant reservoir for a vapor transport type rigid magnetic disk drive lubricant system includes a metal heat sink that presents a finned surface at the side exposed to the outside environment. A second surface within the sealed head-disk enclosure cooperates with a thermal heat transfer resisting wall portion to form a duct. A lubricant reservoir is retained against the heat sink surface within the duct. The reservoir assembly is secured to the head-disk enclosure wall by mounting tape that not only seals the enclosure, but thermally isolates the reservoir assembly from the enclosure wall.Type: GrantFiled: July 19, 1991Date of Patent: August 11, 1992Assignee: International Business Machines CorporatonInventors: John L. Beck, Todd P. Fracek, Nigel F. Misso, Daniel C. Stucky
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Patent number: 4764885Abstract: A minimum parallax stylus detection subsystem is disclosed for use with a graphic input grid overlay which is positioned on the viewing surface of a display device. The invention has a three phase operation wherein, during the first phase, the stylus is at a remote distance from the viewing surface of the display and therefore no representation of the stylus position is displayed. During a second phase, the stylus is brought within a first threshold distance from the viewing surface of the display, during which a cursor image is generated which is precisely positioned on the display corresponding to the detected position of the stylus. During a third phase of operation of the invention, the stylus is brought within a close proximity of the viewing surface of the display, during which the cursor image is removed from the display and an actual trace of the path of the stylus with respect to the graphic input grid overlay is shown.Type: GrantFiled: April 25, 1986Date of Patent: August 16, 1988Assignee: International Business Machines CorporatonInventors: Evon C. Greanias, Karl F. Schroeder, Louis V. Ruffino