Abstract: A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Abstract: An aspect of the invention includes receiving machine learning (ML) training data that includes a plurality of features for a plurality of observations. The ML training data is broken into a plurality of non-overlapping subsets of features and observations. A first ML algorithm is trained based on a first subset of the features and observations, and a second ML algorithm is trained based on a second subset of the features and observations. The training of the first ML algorithm overlaps in time with the training of the second ML algorithm. The first and second ML algorithms are tested. Either the first or second ML algorithm is selected based at least in part on results of the testing. The selected ML algorithm is retained as a trained ML algorithm for predicting one or more of the plurality of features based on one or more others of the plurality of features.

Abstract: A rover includes a base having wheels and a propulsion system coupled to the wheels to propel the rover around a field. A tower is coupled to the base and extends over the base. Sensors are set on the tower and the base and are configured to sense environmental conditions around the rover at different elevations. A computing system includes a processor and memory. The memory is configured to receive measured data from the sensors and determine an amount and manner of water to be dispensed on plant life in the field.

Abstract: An embodiment of the invention provides a method of analyzing an image of a user to determine whether the image is authentic, where a first image of a user's face is received with a camera. Four or more two-dimensional feature points can be located that do not lie on the same two-dimensional plane. Additional images of the user's face can be received; and, the at least four two-dimensional feature points can be located on each additional image with the image processor. The image processor can identify displacements between the two-dimensional feature points on the additional image and the two-dimensional feature points on the first image for each additional image. A processor can determine whether the displacements conform to a three-dimensional surface model. The processor can determine whether to authenticate the user based on the determination of whether the displacements conform to the three-dimensional surface model.

Abstract: A computer determines an intrinsic read speed and an intrinsic write speed associated with a first disk and a second disk. The computer receives a request to read a portion of data, wherein the portion of data is stored redundantly on both the first and second disk. The computer identifies a first latency associated with reading the portion of data from the first disk, where the first latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the first disk. The computer identifies a second latency associated with reading the portion of data form the second disk, wherein the second latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the second disk. The computer determines that the first latency exceeds the second latency. The computer selects the second disk to read the portion of data.

Abstract: Embodiments relate to data shuffling by logically rotating processing nodes. The nodes are logically arranged in a two or three dimensional matrix. Every time two of the nodes in adjacent rows of the matrix are positionally aligned, these adjacent nodes exchange data. The positional alignment is a logical alignment of the nodes. The nodes are logically arranged and rotated, and data is exchanged in response to the logical rotation.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Abstract: A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.

Abstract: A computer system and storage medium that, in an embodiment, prohibit breakpoints from being set within a protected range. In an embodiment, a protected range may be an atomic operation synchronization code range, either based on instructions generated by a compiler or based on source statements that are compiler directives. When a command, such as an add breakpoint command is received, the address of the breakpoint is compared to the protected range, and if the address is within the protected range, the breakpoint is not set. In another embodiment, if the address is within the protected range, the breakpoint is set before the start or after the end of the protected range. In this way, the problems of endless loops may be obviated.

Abstract: A method and system for interlocking a plurality of servers to a server system is disclosed. In a first aspect, the method comprises assigning an identifier to each of the plurality of servers, wherein the identifier associates each of the plurality of servers to the server system, thereby defining a plurality of interlocked servers. In a second aspect, a computer system comprises a plurality of servers, a management module coupled to each of the plurality of servers, and an interlock mechanism coupled to the management module, wherein the interlock mechanism assigns to each of the plurality of servers an identifier that associates each of the plurality of servers to the server system, thereby defining a plurality of interlocked servers.

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.