Abstract: A method for accommodating electronic commerce in a semiconductor manufacturing capacity market. The method comprises the steps of identifying a plurality of players in the semiconductor manufacturing capacity market, each of which players can solicit capacity in semiconductor manufacturing capacity market; providing a neutral third-party, the neutral third party and the plurality of players configured in a hub arrangement for communicating with each of the plurality of players in semiconductor manufacturing capacity trades; and realizing an open market conditionality between each of the plurality of players and the neutral third party so that the semiconductor manufacturing capacity supplied by one or more of the players can be bought and sold among the players; and, the neutral third party can preserve anonymity of each of the plurality of players soliciting semiconductor manufacturing capacity.

Abstract: A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: An object oriented storage pool provides enhanced performance by allowing very fast and efficient allocation of storage elements from the storage pool instead of obtaining a storage element from the heap in an object oriented computer system. The storage pool is preferably in a linked-list format, and operations on the linked list to allocate and return storage elements are atomic operations to assure serialization of accesses to the storage pool. The presence and operation of the storage pool is hidden from the user by overloading the New() and delete() methods that are defined in the programming language. In this manner the storage pool can be introduced without modification to existing application software, thereby enhancing computer system performance without changing other software in the system.

Abstract: A milliactuator integrated with driver and relative position error sensor circuits formed on a single silicon substrate. The integrated milliactuator/electronics module is positioned between the suspension and the slider/transducer assembly to provide rapid, small motion position control of the slider/transducer over data tracks on the disk of a magnetic disk drive. Integration of the milliactuator electronics with the milliactuator reduces parasitic loading and interference problems with the magnetic transducer signals. Electronic circuits are built on a silicon wafer followed by deposition of a planarization layer and a ground plane layer for isolation from the milliactuator which is then built on top of the circuits.

Abstract: A method and apparatus for calibrating a thermal response of a magnetoresistive element is provided. In accordance with one embodiment of the invention, a thermal spacing signal is read using an MR element spaced apart from a surface of a moving storage medium. From the thermal spacing signal a signal value and calibration value are produced. Using the signal value and the calibration value a calibrated signal value is produced. The calibrated signal value may, for example, be compared against a pre-determined threshold to detect surface defects on the storage medium.

Abstract: A process for professional authoring of information about structured domains (i.e., not including fiction) by which authors, as an integral part of the authoring process, provide the data needed to (1) enable intelligent user navigation between the work of different authors without the need for predefined links; (2) enable searches for information based on user context; and (3) identify reuse candidates before information is written and, therefore, minimize duplication. Authors develop concept maps to reflect the structure of the domain rather than the structure of the documentation; define the user context to which a concept map applies; resolve topic intersections between concept maps; define query attributes for articles to be developed; and resolve article intersections identified by means of intersecting query attributes. Computer programs support concept map development, the identification and analysis of topic and article intersections, and association of the data for exploitation in a user interface.

Abstract: A mechanism for setting a conditional breakpoint on all methods called by a specific instance of a class. To set the instance breakpoint, the debugger determines all of the methods that can be applied to the object type or class. In an environment in which full debugging information includes the correspondence between virtual function tables and specific classes, and full class hierarchy information, the methods are located by locating the pointer to the type's virtual function table, and from the virtual function table, locating the specific class in the debugging information. Identifying the specific type permits all of the base classes of the type to be identified in the debugging information, and from the class hierarchy information, all methods for objects of the type can be compiled.

Abstract: A memory interface for an integrated system is presented which allows simultaneous, transparent access to multiple external memories coupled thereto. The memory interface resides within a functional unit of the integrated system and includes multiple memory ports, at least one of which is coupled to dedicated memory and one port to shared memory. The dedicated memory comprises private memory for the functional unit, while the shared memory is common memory coupled to the functional unit and other functional units of the integrated system. The memory interface has a controller for forwarding memory fetch requests generated by requesting units within the functional unit to the proper memory port as determined at system initialization. A lookahead request generator is employed for generating speculative lookahead fetch requests within the memory interface using information on received memory fetch requests and known memory access patterns.

Abstract: A method for implementing a pseudo least recent used mechanism in a four-way cache memory within a data processing system is disclosed. Within a four-way set associative cache memory, each congruence class contains four cache lines. Each congruence class within the cache memory is associated to a least recently used (LRU) field that has four bits. Each of four cache lines within the congruence class is then assigned with a respective set number. The set number of a cache line designated as a least recently used set among the four cache lines is stored in two bits of the LRU field. The set number of a cache line designated as a most recently used set among the four cache lines is stored in another two bits of the LRU field. In response to a determination that the set number of the least recently used set is higher than the set number of the most recently used set, one of the remaining two cache lines that has a higher set number is assigned to be a second least recently used set.

Abstract: The web sharing manager of a receiving sharing client receives duplicated events (e.g. browser requests) and messages from the web sharing manager of a source sharing client that causes the browser of the receiving sharing client to execute the duplicate event/message so that the browsers of the source and receiving sharing client computer system(s) process the same events/messages. Because events/messages, that include control and information locations (addresses), are shared between the source and receiving and sharing client(s), the same web page is simultaneously displayed and controlled, i.e. shared, on all of the sharing client(s).

Abstract: A calibration wafer for precisely aligning a wafer-handling system that processes a plurality of product wafers. The calibration wafer has radial and thickness dimensions and tolerances equivalent to those of the product wafers and further comprises a first center marker adapted for alignment with a second center marker external to the calibration wafer. The calibration wafer may be a component of a wafer center alignment device for precisely aligning a wafer-handling system in a calibration location in relation to a wafer-processing tool, the device further comprising an alignment jig adapted to be repeatably mounted on the tool and on which the second center marker is located. The calibration wafer is adapted to be positioned so that the first center marker aligns with the second center marker.

Abstract: A chip-under-chip module and a substrate for making the module. The module comprises a first larger chip, a second smaller chip attached to the underside of the first chip, a substrate having a top surface to which the first chip is mounted, a cavity into which the second chip fits when the first chip is mounted on the top surface, and an access channel connecting the cavity to the top surface. Underfill is disposed under the first chip between the first chip and the substrate, between the first and second chips, within the cavity, and within the access channel. A process for manufacture of such a module comprises the steps of forming the substrate having the cavity and access channel in the substrate, connecting the first chip to the substrate, and dispensing underfill through the access channel.

Abstract: An Automated Intelligent Network (AIN) telephone system with a central office switching system. The AIN system includes a service provider system for providing customizable subscriber services based upon subscriber-specific data stored in an EMS database. The subscriber-specific data is selectively updated by a service provider. The AIN system further includes an intelligent peripheral system coupled with the central office switching system. The intelligent peripheral system includes a regional relational database for storing regional subscriber-specific data.

Abstract: A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Abstract: A detector and method for detecting data modulated into a timing based servo pattern prerecorded on a media, comprising shifts of pairs of non-parallel transition stripes arranged in a frame of two bursts. Timing intervals between sequential transition stripes are detected. Interval comparison logic compares selected timing intervals and indicates whether the compared intervals represent a “0”, or a “1”. First and second counters respectively increment the number of the compared intervals representing a “0” and representing a “1” in each frame. Bit comparison logic compares, for each frame, the incremented numbers representing a “0” and a “1” to a predetermined criteria and, upon one of the numbers meeting the criteria, identifies the corresponding “0” or “1” as the bit value for the frame. The bits are data comprising longitudinal position words arranged in a linear sequence.

Abstract: A method and system, for improving programs which access a memory array, which accomplish their objects via data-processing equipment programmed to do the following: detect a requested memory operation; determine if the requested operation relates to a preexisting memory array; and execute a dynamic memory management module in a fashion dependent upon whether the requested operation relates to a preexisting memory array. When the requested memory operation relates to a preexisting memory array, the dynamic memory management module does the following: identifies the array element upon which the requested operation is to be performed; determines whether the array element upon which the requested operation is to be performed is a bona fide array element; and, if it is determined that the array element is bona fide, allocates memory for the bona fide array element if such has not been done previously, and performs the requested operation upon the bona fide element.

Abstract: A module is interposed between the operating system and/or applications of a data processing system and the device driver for a graphics adapter within the data processing system. The interposed module may selectively intercept all graphics device driver function requests or simply pass such requests to a device driver supporting specialized (e.g., non-VGA) graphics modes. Standard (e.g., VGA) graphics mode(s) device driver support is accessible to the interposed module. When a specialized graphics mode is selected, the interposed is inactive and passes graphics function requests to the specialized device driver. When a standard graphics mode is selected, the interposed module is active and intercepts all graphics function requests, processing such request with available standard graphics mode support. Change of the graphics mode from standard to specialized or vice versa results in the interposed module changing from active to inactive or vice versa.

Abstract: A latch circuit (10) includes a feedback path which is isolated from a circuit critical path (12). A scan input component (22) is coupled to the feedback path for providing scan test data to the latch circuit (10). A scan output component (23) may also be coupled to the feedback path for providing a separate scan out signal.

Abstract: A method for fabricating a silicon-on-sapphire wafer for processing by silicon-wafer-processing equipment. A layer is deposited on a backside of a silicon-on-sapphire wafer, the layer having optical and electrical properties of silicon, wherein the silicon-on-sapphire wafer may be sensed by a sensor designed to sense a presence of a silicon wafer.