Abstract: An electrical connection assembly for use in computer systems is disclosed. In the preferred embodiment, the computer system contains a backplane circuit card assembly for distribution of electrical signals to one or more pluggable modules. The modules are plugged into the backplane of the computer system without interrupting power to the computer system. The robust power connection is over-rated for the actual current and voltage delivered to the pluggable modules; and if any damage does occur at the point of initial contact, the connector surfaces are wiped beyond the initial contact point to the site of actual electrical contact which can occur at any place on a plurality of redundant surfaces. In this fashion, the connector assembly tolerates the arcing that occurs when the module is plugged into power grid on the backplane.

Abstract: A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier is provided with improved matching characteristics and sense point tolerance under no penalty of performance degradation. The sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A flooding field effect transistor is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor is activated before the sense amplifier is set. The flooding field effect transistor has an opposite polarity of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor provides a charging path to a voltage supply rail. A pair of flooding field effect transistors serve as charging to voltage supply rail elements for silicon-on-insulator (SOI) field effect transistors on each side of complementary bitline structures of the sense amplifier.

Abstract: A debugging apparatus for debugging a particular application, session or transaction in a computer network environment. The environment includes a plurality of clients in processing communication with one another. The apparatus comprises identifying means for identifying a debugging mechanism to the computing environment, a debug table accessible to the debugging apparatus for storing any pertinent information relating to said debugging apparatus, identifying means for identifying at least one client present in the environment. The debug table stores any and all pertinent information about any identified clients as well as whether or not a particular application, session or transaction needs to be debugged. A determining means is also provided for determining if a particular application, session or transaction needs debugging so that debugging operation can be started accordingly.

Abstract: In a direct lid attach structure incorporating thermally conductive material between a lid and an electronic circuit chip, there are provided a number of apertures in the lid. These apertures are provided directly opposite disks or pads disposed on the substrate to which the chip is attached. A hardenable adhesive such as an epoxy is disposed through the apertures and hardened in place so as to provide a bond between the lid and the underlying pad which has been previously affixed to the substrate to which the chip is attached with a compliant adhesive. There is thus provided an electronic chip assembly which allows bonded chip-to-lid thermal interfaces to be used with LGA interconnection techniques. The support structure mitigates the mechanical loads associated with LGA socketing which could otherwise damage the substrate and affect the integrity of the bonded thermal interface.

Abstract: Rapid set-up is achieved in a programmable delay element having identical pairs of positionally corresponding delay stages in parallel arrays. The pairs of delay elements include identical arrangements of circuit elements and are replicable in a step-and-repeat fashion to simplify delay element manufacture for any arbitrary maximum delay time to be provided. Delay stages of the delay element are comprised of multiplexers. Outputs of respective delay stages are simultaneously stored as a signal transition is propagated through the delay stages in a first order to program the delay element. Thereafter, signals are propagated through selected delay stages in a second order controlled by the simultaneously stored outputs of respective delay stages during the propagation of the signal transition.

Abstract: An apparatus is provided for varying the direction which a control laser beam impinges on a rotatable storage medium. The reflected control beam is thus modulated by surfaces aspects of the medium such as by embedded reference tracks. This reflected light signal is converted to an electrical signal which is analyzable to determine vertical alignment particularly with respect to the orthognal direction. In one embodiment, the apparatus comprises a rotating cylinder in which a lens is disposed in a canted orientation so that the optical axis of the lens is not exactly aligned with the axis of the cylinder about which rotation occurs.

Abstract: A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

Abstract: A method is provided for etching and removing extraneous molybdenum or debris on ceramic substrates such as semiconductor devices and also for molybdenum etching in the fabrication of molybdenum photomasks. The method employs a multi-step process using an acidic aqueous solution of a ferric salt to remove (etch) the molybdenum debris followed by contacting the treated substrate with an organic quaternary ammonium hydroxide to remove any molybdenum black oxides which may have formed on the exposed surface of treated molybdenum features in ceramic substrates. The method is environmentally safe and the waste solutions may be easily waste treated for example by precipitating the ferric salts as ferric hydroxide and removing anions such as sulfate by precipitation with lime. The method replaces the currently used method of employing ferricyanide salts which create serious hazardous waste disposal and environmental problems.

Abstract: A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.

Abstract: Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a “fair share” of the bus bandwidth. This share is defined as a number of bytes per a unit of time such as a time period. The shares together total a fraction of the total bus bandwidth, with a margin of bus bandwidth left unassigned. To prevent initiator starvation, each initiator monitors its bus requests to determine if it is being prevented by higher-priority initiators from using its assigned share of the bandwidth. If not, the initiator periodically pings each higher-priority initiator to indicate that it is not being starved. So long as a higher-priority initiator continues to receive pings from all lower-priority initiators, the higher-priority initiator can continue to use as much bandwidth as it needs.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: The head support mechanism is divided into the three portions, i.e. a rear portion one end of which can be pivotally mounted, a front portion supporting a slider including a read/write head for reading data from the magnetic recording disk or writing data to the magnetic recording disk, and a flexible hinge portion connecting the rear portion and the front portion. At least one extruded portion is provided on a surface of the front portion opposing to the recording disk at position adjacent to the flexible hinge portion. The extruded portion is coated by a resilient layer made of a material selected from a group consisting of polyimide, rubber, epoxy resin, silicone rubber, polyvinylchloride, polybutadiene and polyetherurethane.

Abstract: A system and method for uniformly describing space and frequency views of multi-dimensional lattice data, including regions, tilings and hierarchical decompositions of image, video, audio content, and time series data in space, time, frequency and resolution. The space and frequency view description scheme provides a way to specify regions in space, time, frequency and resolution in term of space and frequency views. This allows specification of concepts such as “half resolution”, “upper right quadrant” or “high pass band”, such as when referring to views of an image. The space and frequency view description scheme also provides for SFTilings comprising non-redundant sets of views and SFPartitionings which are SFTilings which completely cover the space, as well as SFHierarchical decompositions comprising hierarchies of SFViews where there are processing dependencies among views.

Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200° C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Abstract: A cryptographic encoded, ticket issuing and collection system for real-time purchase of tickets by purchasers at remote user stations in an information network that includes a plurality of remote user stations coupled to a server in an information network, e.g., the Internet, for purchase of services, products, or tickets to an event. An operator of the remote user station selects a ticket for purchase to an event using standard protocols of information network. An electronic ticket is transmitted to the operator and includes a cypher code created using a public key cryptography system. The operator displays the electronic ticket for verification purposes and proceeds to print out the ticket at the station. The ticket is presented to a ticket collector whereupon the ticket is scanned by a portable terminal for decoding the cypher code using a public key reloaded into the terminal by the producers of the event.

Abstract: A method for optimizing and transforming a compiler program in a computer system. The method comprises the steps of constructing a compiler comprising a program augmentation capability; and, locating this capability in association with phases of a standard compilation process. The program augmentation capability may comprise symbolic automatic differentiation, or generation of Taylor series, or generation of Hessian or Jacobian matrices.

Abstract: A charting metalanguage for uniquely defining a chart to be generated by a computer. The charting metalanguage comprises a plurality of keywords and subkeywords that define the components of the chart. A keyword is preceded by an indicator such as a slash symbol and describes a major characteristic of the chart such as the type of chart, the type of font to be used or the title of the chart. An optional subkeyword follows the keyword. A text and/or data string may follow the subkeyword and/or be positioned between the keyword and the subkeyword.

Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.

Abstract: A charge-pump which substantially reduces transient currents in the switches that connect output control signals to current sources and sinks, to provide improved response for very small phase errors. In a differential embodiment, the charge-pump uses four transistors connected respectively to two current sources and two current sinks, and the reduction in transients is achieved by providing four additional transistors which are connected with the first four transistors to form four pairs of source-coupled transistors. The four pairs of source-coupled transistors are cross-connected to keep the current sources and sinks at constant bias through near-constant conduction, which substantially eliminates any turn-on transients and provides a smoother response.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.