Abstract: A tailorable metallization level between a first set of pads connected to internal circuits of an electronic structure and a second set of pads for external connection provides for altering the configuration of the electronic structure. The second set of pads is kept invariant to facilitate external connection to the electronic structure. The reconfiguration scheme provides, in one embodiment, for sparing a stacked arrangement of chips. That is, it provides a way to disconnect a defective chip from a stack of chips and connect a spare chip so that, from the point of view of external circuitry, there is no change in the connection to or function of the stack. The invention also provides for changing the logical arrangement of circuits in a single chip, such as the organization of memory I/O.

Abstract: A high conductance trap for removing particulates from the effluent of a semiconductor processing system. The trap includes a housing having a gas inlet, a filtering arrangement, and a gas outlet. The gas inlet and gas outlet are arranged in an inline configuration to increase conductance through the trap, thereby enhancing the filtering efficiency of the filtering arrangement. Cooling coils are disposed immediately adjacent the gas inlet to immediately cool the effluent as it enters the trap, thereby further increasing the filtering efficiency of the filter arrangement.

Abstract: A primary data mover monitors both consistency time and idle time in a system that performs continuous, asynchronous, extended remote copying between primary and remote processors, and manages both with accuracy and consistency. The primary data mover detects system activity levels and manages data accuracy for the extended remote copying in both active and idle systems.

Abstract: A method and apparatus are provided for variable spindle rotation speed in a direct access storage device (DASD). The direct access storage device (DASD) includes a multi-phase, brushless, direct current (DC) spindle motor. Speed and commutation control signals are applied to a plurality of spindle motor drivers for normally operating the plurality of spindle motor drivers in saturation mode while performing read and write operations. A spindle rotational speed is detected and compared with a predetermined spindle speed range. Responsive to the detected spindle rotational speed being within said predetermined spindle speed range, normal operations of the direct access storage device (DASD) are enabled. One or more write sync fields are provided on each surface of a magnetic disk media. The write sync field is used for timing write operations in the direct access storage device.

Abstract: Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal lines (20) are located on the memory module substrate (14) and the memory chips (15) are electrically coupled to the memory chip signal lines at spaced apart chip coupling points (23). Digital signals are driven to the memory chip signal lines (20) through signal lines (21) having a first level impedance. The memory chip signal lines (20) have a second level impedance greater that the first level impedance. The spacing between the chip coupling points (23) is chosen such that the effective impedance level of the memory chip signal lines (20) substantially matches the lower, first level impedance.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A system and method for encoding a servo address in a disk drive system having at least one disk for storing data is disclosed. A servo address associated with a sector in a track, or cylinder, on a surface of a disk and comprised of a sector number, a track number, and in multiple disk systems, a head number is encoded into the encoded servo address. Encoding the servo address saves disk storage space because the encoded servo address uses fewer bits than a conventional servo address while still enabling the disk drive system to verify the location of any sector.

Abstract: A database management method enables an improved efficiency processing action in a computer wherein manipulation of data from a table is required in accord with a query request, wherein the table is stored remotely from said computer and at least some data in the table includes large data objects (LOBs). The method includes the steps of: responding to the request by transmitting a query to the table; configuring a result set from the table in response to the query, wherein the result set includes one or more unique identifiers of any LOB data associated with the result set; receiving the result set and performing a data manipulation action on data contained in the result set to form a response; transferring the response to the query requester; and accessing LOB data from the table that is referenced by the one or more unique identifiers in the result set and causing transfer of the LOB data to the query requester.

Abstract: Disclosed is a novel composition of matter comprising a polyacid and a polymer containing repeating units which contain one or more basic atoms. The complex is water-soluble and electrically conductive. The complex is useful in providing organic discharge layers for use in electronic applications and fabrications.

Abstract: Pseudorandom numbers are generated in a cryptographic module in a cryptographically strong manner by combining a time-dependent value with a secret value and passing the result through a one-way hash function to generate a hash value from which a random number is generated. The secret value is continually updated whenever the cryptographic module is idle by a first feedback function that generates an updated secret value as a one-way function of the current secret value and the time-dependent value. In addition, the secret value is updated on the occurrence of a predetermined external event by a second feedback function that generates an updated secret value as a one-way function of the current secret value, the time-dependent value and an externally supplied value.

Abstract: A system for aligning two plates, in accordance with the present invention, includes a first plate having a lithographically patterned structure formed on a first surface. A second plate also has a lithographically patterned structure formed on a second surface, the first and second surfaces being disposed to face each other. The patterned structures of the plates have corresponding and opposing edges to provide an interference fit between the patterned structures of the first and second plates wherein self-alignment between the first and second plates is realized by engaging the corresponding and opposing edges in the interference fit.

Abstract: An apparatus allowing a pair of interrelated C language operations, in particular a setjmp/longjmp and a signal/raise functions to be completed across a plurality of load modules. Upon the issuance of a first instruction or function, such as a setjmp, all information pertaining to the current running processing sub-environment that has been established by a first load module is saved in the memory in any location. Later, upon the issuance of a second and complementary instruction or function, such as a longjmp, issued from a different processing sub-environment established by a different load module, the computer's system stack is searched until the entry for the original processing environment is found. Then once it is established which initial environment the second instruction or function is related to, that information is retrieved from the previously stored memory location and the instruction or function is completed successfully.

Abstract: A method and system for improving communications in data communications networks which provide network emulation. The method and system accomplish their objects via communications equipment adapted to do the following: implant a number of distributed-redundant gateways in an emulated network; and dynamically assign access to operational distributed-redundant gateways. In one embodiment, the network emulation is an Asynchronous Transfer Mode Emulation Local Area Network (ATM ELAN), and the distributed-redundant gateways operate as default Internet Protocol (IP) gateway utilized by LAN Emulation Clients (LE Clients) of the ATM ELAN. Also in one embodiment, the dynamic assignment of access is done such that the data communications loading associated with the default IP gateway is distributed throughout a data communications network.

Abstract: A method and system for determining the best data path in a communication network is presented. A Least Cost Routing path between end users in a multi-network environment, including both public and private networks, is determined based upon a longest prefix match. At network activation time, the numbers or prefixes of numbers of end users attached to the public network (304, 305) are stored in entry node data bases A and C of the private network (303). Assuming an end user terminal U1 calls a target end user U3, an entry node B first checks for a longest prefix match between the called number and numbers already stored into its memory. If this is the first time U3 is called via node B, no match will occur and node B will then broadcast a Query to all nodes in the private network (i.e. Nodes A and C). Only those nodes providing possible access to U3 answer this Query.

Abstract: A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.

Abstract: A system for coding voice signal to optimize bandwidth occupation in a High Speed Packet Switching network while ensuring best voice transmission quality.The voice signal is first encoded using a conventional GSM like RPE/LTP coder providing first sub-frames of coded signal and tagging these first sub-frames as being non-discardable. In addition, a convenient difference between an RPE/LTP provided signal and a corresponding synthesized image is performed (see 36) and is also block encoded into second sub-frames which second sub-frames are tagged as being discardable sub-frames. Said second sub-frames when concatenated to corresponding first sub-frames provide so-called multirate frames. Then, when transmitting said multirate frames over the High Speed packet switching network, dropping discardable tagged data enables solution network congestion situations in any network node and at random with no significant disturbing effect over the voice communication operation.

Abstract: A computer system and method of displaying a source code file with an ordered arrangement of object definitions of multimedia objects selectively display the object definitions in either textual or multimedia representations in response to user input. The representations are inlined within the ordered arrangement of object definitions such that a visual indication of the arrangement of such object definitions in the source code file is maintained. In addition, sets of data are selectively displayed in inlined shorthand notations within the ordered arrangement to permit a user to selectively minimize the representation of a set in a source code file, or to expand the representation of the set for viewing or editing of the specific data in the set.

Abstract: To satisfy host requests, two competing processors self-manage access to a shared resource. Each processor maintains a lock table listing that processor's access state regarding the shared resource. Each processor repeatedly sends the other processor a state announcement message representing the processor's state. These include birth cry, heartbeat, or death knell messages. Whenever certain join-entry conditions apply to a processor, the processor performs a JOIN operation to evaluate and attempt to synchronize its lock table with the other processor's lock table. If data is needed from the other processor's lock table, the processor changes its state announcement message to birth cry. If the processor successfully synchronizes its lock table with the other processor, the JOIN operation dictates DUAL mode for that processor. If the synchronization attempt fails, SOLO results. When JOIN completes, the processor operates in its chosen mode.

Abstract: A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone.

Abstract: An actuator assembly having two coils disposed between the poles of a voice coil motor (VCM) magnet for improved dynamic performance during settling and tracking operations in a disk drive. The two coils in the VCM are connected to separate current sources to allow the current flow in the two coils to have the same sense (clockwise or counterclockwise) or the opposite sense with respect to each other. When the current flows in the two coils have the opposite sense, excitation of the principal in-plane bending mode resonance of the actuator assembly is suppressed allowing the use of an increased servo bandwidth for settling and tracking operations of the disk drive. During seek operations of the disk drive, where maximum torque on the actuator is desirable, the coil currents in the two coils are chosen to have the same sense so that the forces on the actuator from the two coils are additive.