Abstract: A system for cooling of electronic equipment enclosures, the system includes: enclosures with front and rear doors for holding assemblages of electronics; front and rear heat exchangers housed within each of the front and rear doors, respectively; a series of separate supply lines configured with control valves and flow control sensors that provide liquid coolant to each of the heat exchangers; a series of separate return lines configured with temperature sensors for exiting coolant from each of the heat exchangers; separate air purging valves for each of the supply and return lines; a series of spray shields for preventing coolant leaks from entering an inlet airflow, and to protect the assemblages of electronics from coolant leaks; wherein the control valves are actuated by a controller in response to readings from the temperature and flow control sensors to separately control coolant flow to each of the front and rear heat exchangers.

Abstract: System, method and computer program product including instructions executed by a processor system for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. In a semiconductor manufacturing process, the method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain (e.g.

Abstract: Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.

Abstract: Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

Abstract: An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

Abstract: In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

Abstract: A method and system for migrating a UML model across UML profiles. After retrieving a UML model, a source UML element, a source UML profile, a source stereotype, and a source meta-class, the target UML profile, stereotype and meta-class are looked up in a mapping table based on the source UML profile, stereotype, and meta-class. The target UML profile is applied on the UML model. Based on the source meta-class being different from the target meta-class, relationships of the source UML element are retrieved, a target UML element is created, the relationships are copied to the target UML element, and the source UML element is removed from the UML model. The target stereotype is applied to the target UML element. The source stereotype is removed from the target UML element. The source UML profile is removed from the UML model.

Abstract: Techniques for constructing a software application are provided. A data model of the application is represented as a relational model. Control logic of the application is defined to specify each of a plurality of operations of the application as a mapping from a current state of the application data model and one or more current application inputs to a new state of the application data model and one or more application outputs, described by one or more relational algebra operations selected from the group consisting of a relation-complement operation, a disjunction operation and a conjunction operation.

Abstract: Three-dimensional virtual world pattern positioning comprises reading incoming data and utilizing a template system having template nodes that are connected together in a hierarchy to construct the virtual world pattern. Each template node has at least one pattern that the template node can output, a test/criteria to run on the incoming data to determine behavior of the template node and a set of child template nodes to transition to after giving out a pattern. Virtual world pattern positioning comprises calling a first template node to select the virtual world pattern by running the test/criteria on the incoming data, generating a key having a key value, using the generated key value to output a pattern, determining whether the key value also has an associated child template node and providing a reference to the child template node if a child template node exists.

Abstract: Work units are transparently offloaded from a main processor to offload processing systems for execution. For a particular work unit, a suitable offload processing system is selected to execute the work unit. This includes determining the requirements of the work unit, including, for instance, the hardware and software requirements; matching those requirements against a set of offload processing systems with an arbitrary set of available resources; and determining if a suitable offload processing system is available. If a suitable offload processing system is available, the work unit is scheduled to execute on that offload processing system with no changes to the work unit itself. Otherwise, the work unit may execute on the main processor or wait to be executed on an offload processing system.

Abstract: Support sharing resources in a computer system. An operating system within the computer system, the operating system having a kernel level and a user level with the kernel level configured with a first container and a second container. The first container is assigned to a first namespace and the second container is assigned to a second namespace. Both the first and second namespaces are isolated from each other and at the same time in communication with at least one shared object. Communication across the containers is created through a socket in the namespace of the shared object of one or both of the containers. In addition, a conduit is formed between the containers by connecting the container absent the created socket to the container with the socket.

Abstract: Methods of removing material from a defective opening in a glass mold using a laser pulse, repairing a glass mold and a related glass mold for injection molded solder (IMS) are disclosed. In one embodiment, a method includes providing a glass mold including a plurality of solder filled openings; identifying a defective opening in the glass mold; removing material from the defective opening by applying a laser pulse to the defective opening; and repairing the defective opening by filling the defective opening with an amount of solder by: removing a redundant, non-defective solder portion from an opening in the glass mold by applying a laser pulse to the opening, and placing the redundant, non-defective solder portion in the defective opening.

Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.

Abstract: A computer-implemented method of controlling version branching within a software configuration management system (SCMS) can include, responsive to a user initiating a check-out operation of a file within the SCMS, identifying the file and a workspace of the user and searching nodes of the repositories of the SCMS for a successor version of the file. When a successor version of the file is located within a node that is within a predetermined distance of the workspace of the user, a notification that the successor version of the file is within the predetermined distance of the workspace of the user can be output. When a successor version of the file is not located within a node within a predetermined distance of the workspace of the user, the file can be checked-out to the workspace of the user.

Abstract: Systems and methods for transforming a logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Transforming the logical data object comprises creating in the storage device a transformed logical data object comprising one or more allocated storage sections with a predefined size; transforming one or more sequentially obtained chunks of obtained data corresponding to the transforming logical data object; and sequentially storing the processed data chunks into said storage sections in accordance with a receive order of said chunks, wherein said storage sections serve as atomic elements of transformation/de-transformation operations during input/output transactions on the logical data object.

Abstract: A method of managing memory may include selecting an object of a memory heap to be de-allocated and initiating a deferred lock configured to delay de-allocation of the object. The deferred lock may be acquired in response to a thread leaving a computing space, and the object may be de-allocated.

Abstract: A method, a system and a computer program for parallel event processing in an event processing network (EPN) are disclosed. The EPN has at least one event processing agent (EPA). The method includes assigning an execution mode for the at least one EPA, the execution mode including a concurrent mode and a sequential mode. The execution mode for the at least one EPA is stored in the EPN metadata. The method also includes loading and initializing the EPN. The method further includes routing the event in the EPN and, when an EPA is encountered, depending on the execution mode of the encountered EPA, further processing of the event. Also disclosed are a system and a computer program for parallel event processing in an event processing network (EPN).

Abstract: One or more policies to be applied to a set of one or more messages in a message oriented middleware are defined. Metrics of the message oriented middleware are monitored. Application of a policy in response to a trigger condition being satisfied is initiated. Application of the policy applies actions across the set of one or more messages.

Abstract: A method for information processing includes defining a set of abstract operators for use in implementing computing operations, including iterative operations. Respective execution times are determined for the operations implemented by the abstract operators. Given a definition of a rule, including a complex event and an action to be performed upon occurrence of the complex event, software code to implement the rule is automatically generated by generating concrete instances of the abstract operators so as to invoke a sequence of computing steps that includes iterations of the iterative operations. A worst-case estimate of a duration of execution of the software code is computed based on the respective execution times.