Abstract: A computer system including a communication fabric initiates a forced diagnostic to isolate and identify genuine error conditions which are discerned from sympathetic error conditions. Error counters are only incremented for each genuine error condition, precluding the need to set error counter threshold artificially high. Recovery events are logged in a recovery table and recovery actions are only initiated after the diagnoses processes is complete. This prevents duplication of recovery actions and the unnecessary implementation of low-level recovery actions when they will be followed by higher-level recovery actions.

Abstract: A computer implemented method for recovering a partition context in the event of a system or hardware device failure. Upon receiving a command from a partition to modify context data in a trusted platform module (TPM) hardware device, a trusted platform module input/output host partition (TMPIOP) provides an encrypted copy of the context data and the command to the TPM hardware device, which processes the command and updates the context data. If the TPM hardware device successfully processes the command, the TMPIOP receives the updated context data from the TPM hardware device and stores the updated context data received in encrypted form in a context data cache or a non-volatile storage off-board the TPM hardware device. If the TPM hardware device fails to successfully process the command, the TMPIOP uses a last valid copy of the context data to retry processing of the command on a different TPM hardware device.

Abstract: A system and method for enhancing navigation of a topology within a visual display. A system is disclosed including: a system for displaying an enhanced mouse pointer in a current view, wherein the enhanced mouse pointer includes an indicator that points to a resource outside the current view; and a processing system for calculating the indicator by analyzing resources in the topology.

Abstract: A magnetic random access memory (MRAM) device includes a reference magnetic region having a resultant magnetic moment vector generally maintained in a desired orientation without the use of exchange coupling thereto. A storage magnetic region has an anisotropy easy axis and a resultant magnetic moment vector oriented in a position parallel or antiparallel to that of the reference magnetic region. A tunnel barrier is disposed between the reference magnetic region and the storage magnetic region, with the reference magnetic region, storage magnetic region and tunnel barrier defining a storage cell configured for a toggle mode write operation. The storage cell has an offset field applied thereto so as to generally maintain the resultant magnetic moment vector of the reference magnetic region in the desired orientation.

Abstract: A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.

Abstract: A method, apparatus, and computer instructions for responding to a threat condition within the network data processing system. A threat condition within the network data processing system is detected. At least one routing device is dynamically reconfigured within the network data processing system to isolate or segregate one or more infected data processing systems within the network data processing system. This dynamic reconfiguration occurs in response to the threat condition being detected.

Abstract: A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist.

Abstract: When a current synchronization between a first device and a second device is commenced, a last anchor for the current synchronization to an initialization time of a previous synchronization between the first device and the second device, and a next anchor for the current synchronization is set to an initialization time of the current synchronization. Then, a set of data elements to be synchronized during the current synchronization is determined. Typically, the set includes only those data elements that have been modified after the last anchor and up to (e.g., before or equal to) the next anchor. When the set of modified data elements is received on the second device from the first device, a device modified timestamp (DMT) for the set of data elements on the second device is set to the next anchor instead of to the current time at which the data elements are received.

Abstract: A method for selectively cooling one or more heat-generating electronic components in an enclosure. Air is passed through an enclosure that houses one or more heat-generating components. Heated air is separated into at least first and second parallel airstreams within the enclosure. The first airstream is passed through a first heat exchanger in thermal contact with a first side of a thermoelectric cooling module. The second airstream is passed through a second heat exchanger in thermal contact with a second side of the thermoelectric cooling module. A voltage is applied to the thermoelectric cooling module to cool the first side and heat the second side of the thermoelectric cooling module. A temperature at a location in the enclosure in sensed and the voltage applied to the thermoelectric cooling module is varied in response to the sensed temperature.

Abstract: An apparatus, system, and method are disclosed for booting a Logical Partition using an external storage device. The method creates a virtual SCSI device assigned to a first logical partition (“LPAR”) of a first computer using a virtual I/O server by mapping a LUN of a storage volume to a SCSI ID. The storage volume is located external to the first computer and the first LPAR is configured to share one or more physical processors and one or more physical I/O devices of the first computer with a plurality of LPARs. The method receives a boot request to boot the first LPAR. The boot request identifies the storage volume as a boot device using the SCSI ID of the virtual SCSI device. The method retrieves boot data from the storage volume using a SCSI driver of the first LPAR and boots the first LPAR using the boot data.

Abstract: A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.

Abstract: A method, apparatus, and computer instructions for programmatically generating synthetic transactions to monitor performance and availability of a Web application. The mechanism of the present invention may be implemented as a Java 2 Platform Enterprise Edition (J2EE) transaction, wherein the J2EE application is instrumented with just-in-time-instrumentation (JITI). A JITI probe determines if a customer request object contains a cookie. If not, the JITI probe inserts a cookie into the response object. The cookie is used to track URIs visited by the customer. An algorithm is used to identify the baseline customer transaction path based on the URIs in the cookie. All baseline customer transaction paths for all customers are then correlated to form a unique transaction, wherein the unique transaction comprises the most common tasks performed in the Web application. The Web application may then be monitored by programmatically recording and scheduling playback of the unique transaction.

Abstract: Memory systems are disclosed that include a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module, where memory module includes a memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, with the high speed memory bus connected to the memory hub device by a negligible electrical stub.

Abstract: Methods, systems, and computer program products are provided for prefetching and caching portal information in a client application in a logically separated client/server computing environment. Before a user requests a specific portlet view to be displayed at the user's web browser, portlet information from a server is prefetched. The portlet information may include content data to be displayed in a portlet view, meta data describing how the content data will be displayed, and combinations of both content data and meta data. The prefetching step is performed on the client of the logically separated client/server computing environment. The client stores the prefetched portlet. Once the prefetched portlet information has been stored, upon a user request such as clicking on a link in a portlet view, the method retrieves the stored portlet information and displays the portlet information in a corresponding portlet view.

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract: An apparatus, program product and method stripe value data associated with each of a plurality of keyed data sets across a plurality of processes in a data process set and accessing a first keyed data set among the plurality of keyed data sets using at least one of the plurality of processes. Value data is striped by dividing a keyed data set among the plurality of keyed data sets across the plurality of processes in the data process set based on a striping strategy.

Abstract: A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a single part number. A non-volatile storage is provided on a part, wherein the part includes a plurality of sub-components. Unavailable sub-components in the plurality of sub-components are identified based on a series of testing to form identified unavailable sub-components. Information of the identified unavailable sub-components is stored into the non-volatile storage.

Abstract: Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. In a first aspect, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for use by a special class of threads, and can not be used by other threads even if idle. In a second aspect, the special class of threads can fill only the a limited portion of the cache memory, in order to reduce flushing of the cache which might otherwise occur.

Abstract: A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register.