Patents Assigned to International Business Machines for Corporation
  • Patent number: 11055015
    Abstract: A method for suppressing data mirroring between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes defining a data class with an attribute designed to suppress mirroring of data from a primary storage system to a secondary storage system. The method assigns a data set to the data class, thereby causing the data set to inherit the attribute. In certain embodiments, assigning the data set to the data class includes recording the attribute in one or more of a volume-table-of-contents (VTOC) and a catalog used to reference the data set. The method automatically suppresses mirroring of the data set from the primary storage system to the secondary storage system in accordance with the assigned attribute. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Harry M. Yudenfriend, John R. Paveza, Peter G. Sutton, Tan Q. Nguyen, Gerard M. Dearing
  • Patent number: 11056426
    Abstract: Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Hosadurga Shobha, Hsueh-Chung Chen, Chih-Chao Yang
  • Patent number: 11055330
    Abstract: A computer-implemented method for utilizing external knowledge and memory networks in a question-answering system includes receiving, from a search engine of a question-answering system, one or more search results based on a search query associated with a question submitted via a user interface associated with a computing device, analyzing the one or more search results to generate search evidence as a source of external knowledge for generating an answer to the question, the search evidence including one or more titles and one or more corresponding text snippets, encoding the search evidence and the search query to generate vectors stored in a memory network, obtaining a final vector representation based on the encoding, and decoding the final vector representation to obtain the answer to the question.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Wang, Shi Lei Zhang, Wen Liu, Feng Jin, Qin Shi, Yong Qin
  • Patent number: 11055017
    Abstract: A computer-implemented method according to one embodiment includes determining that a consistency group has not been created within a predetermined period of time; sending a request to create the consistency group, where the request includes an indication that a creation of the consistency group is mandatory; identifying one or more logical storage volumes associated with the request to create the consistency group; marking each of the identified one or more logical storage volumes to indicate that a point-in-time snapshot copy operation is not allowed for the one or more logical storage volumes; creating the consistency group; sending the consistency group from a source site to a destination site; and removing the marking from each of the identified one or more logical storage volumes to indicate that a point-in-time snapshot copy operation is allowed for the one or more logical storage volumes.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Ward, Theresa Mary Brown, Nedlaya Yazzie Francisco, Gail Spear
  • Patent number: 11056132
    Abstract: In one embodiment, an apparatus includes a module having a substrate and a closure, an array of transducers in a thin film structure on the substrate, the array being positioned along a tape bearing surface of the module, and a heating element positioned in the thin film structure and recessed from the tape bearing surface, and a controller electrically coupled to the heating element. The controller is configured to apply a current pulse of size, shape and duration sufficient to induce a permanent expansion of the array of transducers.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Hugo E. Rothuizen, Calvin S. Lo
  • Publication number: 20210200891
    Abstract: Embodiments relate to a computer system, computer program product, and method to prevent unauthorized file dissemination and replication. A file parameter is defined, with the defined file parameter including a file dissemination characteristic. The file is encoded with the defined file parameter as file metadata. Dissemination and replication of the file is managed responsive to the encoded file parameter. The defined parameter is assessed along with a physical replication destination. The file is selectively replicated or transmitted responsive to the file parameter and the destination assessment.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven R. Welch, Sandeep Gopisetty, Chad Eric DeLuca, Christian B. Kau, Anna Lisa Gentile, Daniel Gruhl, Linda Ha Kato, Alfredo Alba
  • Patent number: 11049830
    Abstract: An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chad Andrew Marquart, Daniel M. Dreps
  • Patent number: 11049139
    Abstract: At least one configured mobile device monitoring radius relative to respective purchase locations is established within a retail environment. Mobile device distances from purchase locations at times of purchases within the retail environment are monitored over time by a processor utilizing locationing technology. A repeating mobile device proximity pattern of at least two mobile device identifiers being located together and in proximity to the respective purchase locations at the times of the respective different purchases is detected across the several different purchases.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dmitri S. Dodor, Jeffrey R. Pratt, Kyle D. Robeson
  • Patent number: 11049035
    Abstract: Techniques and a system to facilitate meta-level quantum computation are provided. In one example, a system includes a quantum processor and a classical processor. The quantum processor can perform an expectation computation process to compute an expected value of a deflated operator and a quantum state associated with a quantum circuit description. The classical processor can execute computer executable components stored in a memory, where the computer executable components comprise a meta-level variational optimization component. The meta-level variational optimization component can perform a meta-level optimization process associated with a k-eigenvalue decomposition process to iteratively determine an inflation parameter and a variational parameterization for an eigenpair based on samples of the expectation computation process.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lior Horesh, Giacomo Nannicini
  • Patent number: 11047907
    Abstract: A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Mohit Kapur
  • Patent number: 11048500
    Abstract: A change to a collaborative data repository made by a developer is detected. Using an analysis of the change, a change score corresponding to the change is computed, wherein the analysis comprises determining a complexity score of the change, a writing quality score of the change, a value score of the change, and a criticality score of the change. Using an analysis of the developer, a first developer score is computed, wherein the analysis comprises determining a role score of the developer and a history score corresponding to a previous change of the developer. Based on the change score and the first developer score, a restriction on implementing the first change is enforced. A result of the change and the restriction is detected. Based on the result, the change score, and the first developer score, a second developer score is generated.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Huntington Grant, Zachary A. Silverstein, Shikhar Kwatra, Amanda Nicole Wilk
  • Patent number: 11048703
    Abstract: Provided are techniques for minimizing processing using an index when non-leading columns match an aggregation key. A query that includes a clause and an aggregation key is received. It is determined that a non-leading key column of an index matches a column of the aggregation key comprising any of: a leading column of an ORDER BY aggregation key, any column of a duplicate removal aggregation key, a MIN aggregation key, and a MAX aggregation key. The clause is processed using an order of the aggregation key to generate a first result set. Then, the clause is processed using the non-leading key column of the index that matched the column of the aggregation key and the first result set to generate a second result set. The second result set is returned.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Terence P. Purcell, Thomas A. Beavin
  • Patent number: 11048689
    Abstract: An example operation may include one or more of connecting, by a scheduler node, to a blockchain network comprised of member nodes, receiving, by the scheduler node, a plurality of transactions that include deadlines from the member nodes, comparing, by the scheduler node, the deadlines of the plurality of the transactions against an average time to append to a ledger (ATAL) pre-calculated for the scheduler node, dropping, by the scheduler node, the transactions of the plurality of the transactions, if a sum of the ATAL and a current time is larger than the deadlines of the plurality of the transactions, calculating, by the scheduler node, a priority usage balance (PUB) for the member nodes based on the transactions of the plurality of transactions remaining after the transactions of the plurality of the transactions have been dropped, scheduling, by the scheduler node, a transaction with an earliest deadline from the plurality of the remaining transactions to be validated first for an execution, and arrangin
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Konstantinos Christidis, Nitin Gaur
  • Patent number: 11050773
    Abstract: Prioritizing security incidents for analysis is provided. A set of security information and event management data corresponding to each of a set of security incidents is retrieved. A source weight of a security incident and a magnitude of the security incident are used to determine a priority of the security incident within the set of security incidents. A local analysis of the security incident is performed based on the retrieved set of security information and event management data corresponding to the security incident and the determined priority of the security incident.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen C. Will, Kevin Tabb, Ilgen B. Yuceer, Sulakshan Vajipayajula, Kaushal K. Kapadia
  • Patent number: 11048846
    Abstract: Techniques regarding an autonomous surface participation analysis of one or more superconducting qubits using the boundary element method are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a simulation component, operatively coupled to the processor, that can analyze a surface participation of a superconducting qubit by discretizing a conductor-dielectric interface and a dielectric-dielectric interface into a plurality of panels.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Firat Solgun
  • Patent number: 11048627
    Abstract: Provided are a computer program product, system, and method for determining the location for volumes of data being initially stored within a storage space, regardless of the physical location of the data. The storage space includes stripes composed of volumes, which can be logically represented as a utilization histogram of stripe locations offset from one another. Sometime the stripes are fully allocated with one large volume or partially allocated with multiple, arbitrary-sized smaller volumes. When there are multiple smaller volumes that do not utilize all of the available stripe space, gaps form. To minimize the creation of such gaps, when a volume of data is initially stored, a start location to place the volume of data is selected by using selection criteria as guidance.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventor: Michael Keller
  • Patent number: 11049933
    Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh
  • Patent number: 11048839
    Abstract: A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Gunnels, Mark Wegman, David Kaminsky
  • Patent number: 11049940
    Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Heng Wu
  • Patent number: 11048803
    Abstract: A method, apparatus, system, and computer program product for operating a portable security testing device. The portable security testing device is configured by computer system with an operating system and a starting set of security testing tools. A selected set of the security testing tools is determined by the computer system for the portable security testing device based on information collected about a target by the portable security testing device. The starting set of the security testing tools in the portable security testing device is changed by the computer system to form a current set of the security testing tools in response to the starting set of the security testing tools being different from the selected set of the security testing tools, wherein the current set of the security testing tools operate to perform security tests on the target.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jason A. Nikolai, Steven Ocepek, Johnny Al Shaieb