Abstract: A method and system for preserving message order when parallel processing messages by: providing a marker (H) in each message (M) for identifying a source of messages for which it is required to preserve the message order; and dispatching (D) each message in accordance with its marker to one of a plurality of parallel processors (P1-P3) so that processing is preserved for messages processed through the plurality of parallel processors. The dispatcher (D) retains a list of all markers of messages that are being processed in parallel, and when a message becomes available to the dispatcher for processing, the dispatcher inspects the list of messages that are currently being processed to determine whether the marker of this message is in the list, and if so delays initiating parallel processing for this message until the marker is no longer in the list.

Abstract: A method for performing coverability analysis in software, including performing a static analysis of software under test (SUT) so as to identify a plurality of dominating blocks in the SUT, formulating respective coverability tasks for the dominating blocks of the SUT and generating rules regarding behavior of the SUT corresponding respectively to the coverability tasks. The method further includes, for each of the rules, running a symbolic model checker to test a behavioral model of the SUT, so as to produce respective results for the rules, and computing a coverability metric for the SUT responsive to the results and the coverability tasks.

Abstract: A method, system, and program for estimating hold queue wait times are provided. Call times are individually estimated for multiple calls within a call center. In particular, call times may be estimated according to representative profiles, caller profiles, and current caller activity of the multiple calls within the call center. The identity of each caller may be authenticated and a caller profile accessed from a central server according to authenticated caller identities. The central server may be accessible to multiple call centers, where each call centers accesses and updates caller profiles according to a single caller identifier for each caller. In addition, call times estimates and factors utilized to calculate call time estimates may be output to a caller, preferably according to an output interface specified by the caller in the caller profile.

Abstract: A method, apparatus, and computer implemented instructions for enforcing power-off or operating mode change in personal electronic devices. The present invention causes a personal electronic device to change to a required operating mode as indicated by a broadcasted signal in a venue that restricts access of personal electronic devices. Additionally, the personal electronic device can reset to a previous operating mode, i.e., the operating mode prior the enforced change upon receipt of an appropriate broadcast signal.

Abstract: A method, system, and program for promoting caller voice browsing while a caller is waiting in a hold queue are provided. At least one web page is selected for voice browsing by a particular caller waiting in a hold queue. The particular caller may be offered an incentive to voice browse the at least one web page, such that an on hold system housing the hold queue may promote voice browsing of specific web pages. Incentives may be in the form of points that are redeemable by the caller, for example, for adjustments in position within the call queue. In addition, the identity of the caller is preferably authenticated and a caller profile accessed according to the authenticated caller identity. Voice browsing web page selections may be tailored for the caller according to the caller profile.

Abstract: Debugging of a transaction across multiple processors is facilitated by having debug information follow the transaction from processor to processor. The transaction can be debugged across processors without predefining the transaction path, and without performing a debug registration process between the client controlling the debugging and each processor of the multiple processors.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows “field selection” of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified.

Abstract: A system and method is disclosed for simultaneously testing columns and column redundancies of a semiconductor memory by temporarily adding an additional parallel signal bit to an input/output data bus associated therewith, the additional parallel signal bit providing greater bandwidth during test mode operation. The input/output data bus has n parallel signal bits which normally carry column data, but the additional parallel signal bit does not normally carry either column data or column redundancy data. The additional parallel signal bit may normally carry a clock signal such as an echo clock associated with the data placed on the data bus.

Abstract: A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.

Abstract: A method and a corresponding system for controlling multiple notes are disclosed. A multiple note (340) includes a series of (basic) notes (330,335) that have been forwarded by other users. In the proposed representation, the basic notes are arranged in a tabbed pane (345). The tabbed pane consists of multiple overlying panels (350) resembling a stack of pieces of paper lying on top of one another, with only the topmost panel that is visible to a user; a selection tab (355) is attached to each panel. Each panel and the corresponding tab are associated with a respective basic note; particularly, the panel is used to display the basic note, whereas the tab is denoted with the first characters of the subject identifying the corresponding basic note. Therefore, whenever the user wishes to view a desired basic note, he or she simply selects the corresponding tab in order to pop up the respective panel.

Abstract: A method, system and apparatus for generating an XML document to represent network protocol packet exchanges are provided. Each data packet consists of different internal fields. The fields are identified are used to generate the XML document. Specifically, the different fields are used as tagged element of the XML document.

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

Abstract: Exemplary embodiments typically include methods of deploying a predefined data warehouse process model from a development system having a development environment to a customer system having a customer environment, the customer environment being different from the development environment. Embodiments typically include exporting metadata from the predefined warehouse process model to an interchange metadata file, in which the metadata comprises data elements describing a development environment, in which the metadata comprises at least some data elements having values that are site dependent, and copying, from the interchange metadata file to an interchange resource file, site dependent data elements. Embodiments typically include identifying site dependent data values of the customer system, converting, in the interchange metadata file, the site dependent data element values to the site dependent data values of the customer system, and importing the interchange metadata file into the customer system.

Abstract: A shrouded hard disk drive includes one or more contamination filter cavities embedded within the shroud for capturing airborne contaminants circulated within the drive during normal operation. The present invention takes advantage of naturally occurring radial and circumferential velocity differences between air at the edges of the disk pack and the air at the filter cavity entrance opening (i.e., the inner circumference of the shroud) to redirect airflow through a filter positioned within the one or more filter cavities. After air passes through the filter, it exits through a filter cavity exit opening positioned in proximity to either in the area between the disks, or the area above or below the disk pack.

Abstract: During scan testing of logical and memory circuits, it is important to prevent a scan test error resulting from simultaneous switching of the values within chip logic. Scan testing, however, encompasses rapidly scanning in values into a register to detect if the register is properly functioning. A circuit is disclosed which looks at the n−1 values within the register and determines if the next scan in value would cause contention. If so, that value is blocked until the next scan in value would not cause contention with the n−1 values within the register. Practicably, the invention will allow only allowed values into the register and may allow a “hot one” value into the register every n−1 clock cycle. Feedback of the values in the register is provided to a logical AND function to determine if a differing bit value will be allowed to scan into the register.

Abstract: A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal.

Abstract: A method for generating program source code of a computer application from an information model representing a high level specification of the computer application, comprises a step of inserting reconciliation annotations in the program source code, the reconciliation annotations representing a modification rule and a modification state for each language element contained in the generated source code. Then, upon receiving a current version of the program source code, the current version resulting from the modification by a user of an old generated version of the program source code, and a new generated version of the program source code, the new version reflecting changes in the application information model, a step of reconciling the current version with the new version of the program source code according to the reconciliation annotations inserted in each of the current and new program source code versions, and a step of generating a reconciled version of the program source code are performed.