Abstract: Methods and apparatus for compensating offsets in a read signal generated by a sensor associated with a probe of a local-probe data storage device during read-scanning by the probe of bit-positions on a storage surface. An apparatus comprises a generator for generating an offset compensation signal, and a subtraction stage for producing an output signal dependent on the difference between the offset compensation signal and the sensor read signal at each bit-position. In some embodiments, an offset signal generator generates an offset compensation signal dependent upon a predetermined measurement of the sensor read signal. In another aspect the offset signal generator low-pass filters the sensor read signal during read scanning to generate the offset compensation signal. Particular embodiments also include a secondary offset compensation stage for applying additional offset compensation techniques to the output signal from the subtraction stage.

Abstract: A color filterless display device performing color display for expressing one pixel by three RGB sub-pixels includes: a light source; a diffraction grating for separating a light irradiated from this light source into lights of a plurality of wavelength regions; a cylindrical lens array for receiving the separated light and condensing the light while corresponding to each of the sub-pixels; and a liquid crystal cell including a structure portion for correcting an angle of the condensed light for all sub-pixels, wherein, in the structure portion of this liquid crystal cell, a side onto which a light from the cylindrical lens array is made incident is made of a high refractive index layer, an emitting side from which the light is emitted is made of a low refractive index layer, and a Fresnel-type microprism structure is formed by the high refractive index layer and the low refractive index layer.

Abstract: A method and apparatus for providing efficient management of LRU insertion points corresponding to defined times-in-cache is disclosed. Insertion points are implemented as “dummy entries” in the LRU list. As such, they undergo the standard process for aging out of cache, along with all other entries. A circular queue of insertion points is maintained. At regular intervals, a new insertion point is placed at the top of the LRU list, and at the tail of the queue. When an insertion point reaches the bottom of the LRU list (“ages out”), it is removed form the head of the queue. Since insertion points are added to the list at regular intervals, the remaining time for data at the corresponding LRU list positions to age out must increase in the same, regular steps, as we consider insertion points from the bottom to the top of the LRU list. Therefore, we can find an insertion point which exhibits any desired age-out time, by indexing into the circular queue.

Abstract: The invention relates to a process for forming bilayer resist images with a chemically-amplified, radiation-sensitive bilayer resist. The bilayer resist is disposed on a substrate and comprises (i) a top imaging layer comprising a radiation-sensitive acid generator and a vinyl polymer having an acid-cleavable silylethoxy group and (ii) an organic underlayer. The bilayer resist is used in the manufacture of integrated circuits.

Abstract: The invention concerns multimedia kiosk (newsstand) systems where single system units are interconnected via a telecommunication network. The objective is to enable updating of all information and/or the network interconnection structure between the system units during run-time.The invention solves this problem, by common dynamic management of both the configuration data and the information contents in an object-oriented database. The provision of all system functionalities as an object-oriented database enables the kiosk contents in an individual kiosk to be updated, or configuration data, e.g. network addresses to be notified-during run-time. For updating it is only necessary to transfer a so-called "version file" at a particular point in time to one or more terminals via the network. The database operations indicated in the version file are then executed at the terminal in the background, step by step.

Abstract: In a computer system having a processor, memory, and a set of storage units storing a set of objects, each object comprising a set of segments arranged in a set of original object stripes on separate storage units, a directory is maintained identifying an object name and a location of each stripe of the object in the set of storage units. A method is provided for re-striping the set of objects onto an expanded set of storage units comprising the set of storage units and at least one other additional storage unit. A list is maintained of each object to be copied onto the expanded set of storage units. Each segment is copied to a new set of stripes on a separate storage unit of the expanded set to create a new object while continuing to store an original copy of each segment of the list object in the original set of object stripes. The directory is updated to include a new object name and a new location of each new stripe of the new object.

Abstract: A method is described for finding correlation between a plurality of data having two kinds of numerical attributes and a true-false attribute. The method comprises the steps of: constituting a plane with two numerical attributes, dividing the plane into meshes, and counting the number of data in each mesh (also called a "bucket") and the number of data whose true-false attribute represents true. If each mesh is assumed to be a pixel, such plane can be considered as a plane image in which the number of data corresponds to brilliance, and the number of data whose true-false attribute represents true corresponds to saturation. The method further includes the step of segmenting an admissible image which is convex along an axis of the plane according to a predetermined condition .theta. to find an area with strong correlation. If the segmented area as the admissible image satisfies the above-described condition such as the maximized support rule, the method also presents the area to the user.

Abstract: A CMOS current reference is provided that is relatively independent of supply voltage and generates a substantially steady current. The current reference includes a plurality of P-channel FETs and a plurality of zero threshold voltage N-channel FETs that provide a high level of voltage supply rejection at relatively low supply voltage levels (1.5 to 3.3 volts). Utilization of the P-channel FETs and the zero threshold voltage N-channel FETs in a current mirror and cascade configuration reduces the sensitivity of the current to variations in the supply voltage. The current reference exhibits higher offset voltage capabilities. In addition, the CMOS current reference may be designed to compensate for process variations since the current will increase as the channel length of the zero threshold voltage N-channel FETs increases.

Abstract: A memory controller generates control and address signal for accessing a non-volatile memory having a plurality of addressable cells. Each cell of the non-volatile memory includes a floating gate transistor (e.g., Q15) capable of storing charge (representing a binary 1 or 0) for extended, although not indefinite, periods of time. To refresh any charge that leaks off the floating gate, refresh circuitry (e.g., Q17-Q19) is provided to restore the charge on the gate to its original logical state. This refresh circuitry may be activated at "power-up." Each of the transistors in the memory are preferably thin film, amorphous silicon, "N" type transistors, including the floating gate transistor.

Abstract: To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time. An address control scheme was introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU. Command processing section 34 always prepares memory blocks and sectors for writing or erasing and copying in preparation for the command processing of the host CPU, and records and holds the correspondence relation between the physical address of the selected memory block 32i or sector and the command of the host CPU in address conversion table 36.

Abstract: A method and system for reducing perplexity in a speech recognition system based upon determined geographic location. In a mobile speech recognition system which processes input frames of speech against stored templates representing speech, a core library of speech templates is created and stored representing a basic vocabulary of speech. Multiple location-specific libraries of speech templates are also created and stored, each library containing speech templates representing a specialized vocabulary for a specific geographic location. The geographic location of the mobile speech recognition system is then periodically determined utilizing a cellular telephone system, a geopositioning satellite system or other similar systems and a particular one of the location-specific libraries of speech templates is identified for the current location of the system.

Abstract: A driver circuit has hysteresis. The driver circuit includes a comparator circuit having first and second inputs and an output. The driver circuit also includes a variable voltage divider circuit coupled between the second input and the output of said comparator. The voltage divider circuit provides a first voltage to the second input of the comparator when the output of the comparator is at a second voltage, and a third voltage to the second input of the comparator when the output of the comparator is at a fourth voltage. Therefore, the output voltage of the comparator switches from the second to the fourth voltage when the voltage of a signal at the first input of the comparator rises above the first voltage, and the output voltage of the comparator switches from the fourth to the second voltage when the voltage of the signal at the first input of the comparator falls below the third voltage.

Abstract: Power management interrupt enabling is done after completion of POST by loading either DOS or OS/2 operating systems in accordance with whichever operating system the computer is setup to operate under. After being loaded, the operating system then enables the PMIs. This provides a very simple solution that allows the PMIs to be used in a computer operable under a plurality of operating systems.

Abstract: A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.