Abstract: Administering correlated error logs in a computer system having a system controller and one or more redundant node controllers including providing by the system controller to a redundant node controller a unique identifier for error logs; detecting by the system controller a communications failure between the system controller and the redundant node controller; in response to detecting the communications failure, generating by the system controller a system controller error log for the communications failure including the unique identifier; detecting by the redundant node controller the communications failure between the system controller and the redundant node controller; and in response to detecting the communications failure, generating by the redundant node controller a redundant node controller error log for the communications failure including the unique identifier.

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

Abstract: A load balancing method and system for identifying an input/output (I/O) network path from a set off I/O network paths is provided by the invention. The set off I/O network paths connect a host system via a network to a storage subsystem. The host system comprises at least one host bus adapter (HBA) and the storage subsystem comprises at least one I/O device and the network comprises at least one network device. Each of the HBA, the I/O device and the network device comprise at least one I/O port. For each I/O port of each HBA, an HBA port limit is determined. Additionally the set of I/O network paths which connect the I/O port of each of the HBA via the I/O ports of the network device to the I/O port of the I/O device is identified. Then a fabric utilization limit is determined for each I/O network path and a HBA port utilization is determined for each I/O port of the at least one HBA. All network paths are discarded for which the HBA port utilization is greater than the HBA port limit.

Abstract: A self-adaptive resource management method and a corresponding system. An authority publishes multiple rules into a corresponding repository. Each rule defines a desired target configuration for a category of subjects. Some rules are also associated with a corresponding stage in a predefined flow of application of the rules. A supervisor publishes the value of a current stage into a workflow repository. Each subject retrieves and applies the rules for its category and corresponding to the current stage. Information about the compliance of the subjects with the corresponding rules is published in a membership data repository. The supervisor detects the completion of the current stage when the subjects are compliant with the corresponding rules, and updates the value of the current stage to start a further stage.

Abstract: Systems and media for reconstructing data from simulation models are disclosed. Embodiments may include a media containing instructions for accessing an alias from an alias file. The media may include instructions for searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The instructions may also include, if the net name entry is found, instructions for accessing from an alias file an alias associated with the net name. A further embodiment may include instructions for receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.

Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.

Abstract: Routing data packet traffic in packet networks, expediting the flow of the data packets and reducing the effects of congestion at nodes is accomplished by capturing latency data for nodes for initial measurement times; and computing a least squares estimate of the delay as a recursive least-squares solution.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.

Abstract: An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment.

Abstract: Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Abstract: A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.

Abstract: A method for providing an alert indication, the method includes: allowing a first user to define an alert to be generated in response to an availability of a second user to participate in an instant messaging session; and sending to the second user an alert indication indicative of the alert.

Abstract: The invention discloses a method for specifying Web service behavior that includes a step of exposing an internal logic flow of a Web service to clients. The internal logic flow can include at least one activity, which is defined by a set of machine-readable instructions. A special invocation command for the Web service can be received from a client. The special invocation command can specify a modification for the activity. An instance of the Web service can be invoked for the client, where the Web service instance implements the modification instead of the activity.

Abstract: Methods and arrangements to monitor communication components such as a network adapters for activity, and identify components that have lower than normal levels of activity are provided. An identified communication component can become suspect component and a candidate for further testing, including different forms of interrogation. Process for interrogating candidates can include generating and sending test packets having the media access control (MAC) address of the candidate to the candidate and if activity is not detected subsequent to the interrogation, the candidate can be flagged as a failed component. Correspondingly, the component can be deactivated and removed from service. In a further embodiment, a backup component can be activated and assume the role previously held by the failed component.

Abstract: A system and method implemented by a computer for performing query based electronic document retrieval implementing a Markov process model adapted for determining a relationship or relevance between documents. The system ranks documents for retrieval based on their relevance measure. The model calculates the measure of relevance that a document from a given database is relevant to a given query. The method learns the Markov models mixture coefficients from the document database so as to maximize the relevance measure of the documents being retrieved. The method requires only that a similarity measure, D(d,d?), between two documents be specified. Any existing method may be used for generating a model that is at least as good as the chosen similarity measure.

Abstract: The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.

Abstract: Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro.

Abstract: The present invention is directed to soldering techniques and compositions for use therein. In one aspect, a flux composition is provided. The flux composition comprises a fluxing agent comprising organic acid, an organic tacking agent and an organic wetting agent. In another aspect, a soldering method for joining objects is provided comprising the following steps. A flux composition and a solder compound are applied to at least a portion of one or more of the objects. The flux composition comprises a fluxing agent comprising organic acid, an organic tacking agent and an organic wetting agent. The objects are then joined.

Abstract: A start-up circuit for a high voltage power distribution circuit includes a transistor, a current source which generates ramped current, an operational amplifier which is connected between the current source and the transistor and controls the transistor, a capacitor which is fed the generated ramped current from the current source and is charged by the generated ramped current, the capacitor being connected to the non-inverting input of the operational amplifier, and a feedback capacitor connected from the transistor output to the non-inverting input of the operational amplifier, which is fed the generated ramped current from the capacitor and is discharged. The transistor is fully enabled when the feedback capacitor is fully discharged.