Abstract: A method and associated systems for automatically generating an ontology and a set of axioms from a business-process model that represents the operations of a business. This ontology and set of axioms may be used to create the knowledgebase of an artificially intelligent expert system that emulates the business operations. A processor parses a representation of business processes stored in the business-process model, deriving a set of axioms and a set of entity classes from the parsed data. The processor uses these axioms and classes to identify concept nodes and process nodes, which it organizes into the ontology of the knowledgebase. The processor further identifies information derived from the parsed data to create a set of triple data items, each of which represents the information represented by one or more of the derived axioms. These triples are stored in the knowledgebase as a triple store data structure.

Abstract: An apparatus comprises a memory and a processor device operatively coupled to the memory. The processor device is configured to select one or more constituents and one or more classes of work products, analyze one or more existing work products to identify constituents frequently combined with the selected constituents and to identify constituents frequently used to create work products in the selected classes, determine a set of constraints for combining constituents for the set of classes based at least in part on a result of the analyzing step and generate one or more new work products in the set of classes using the set of constraints.

Abstract: The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

Abstract: In one embodiment, a method includes determining that a request to allocate a target data set on a first storage includes a release command, determining an actual size of the target data set after storing the target data set on the first storage, comparing the actual size of the target data set to a break point value, relocating the target data set from cylinder-managed storage to track-managed storage of the first storage when the actual size of the target data set is less than the break point value and the target data set is stored on the cylinder-managed storage, and relocating the target data set from the track-managed storage to the cylinder-managed storage of the first storage when the actual size of the target data set is at least as great as the break point value and the target data set is stored on the track-managed storage.

Abstract: A method, computer-readable storage medium, and computer system are provided. In an embodiment, begin installation of a first program product with an installation manager. Poll the first program product to determine whether an operation milestone has been reached during the installation of the first program product. Upon detecting an operation milestone, performing the parallel operation substantially concurrent with the installation.

Abstract: Computer-aided translation systems include a processor configured to generate a suggestion pool of possible translations for each sentence in a document that has one or more sentences to be translated; a translation module configured to provide a best suggestion from the suggestion pool to a user for a sentence being translated and to provide an updated best suggestion from the updated suggestion pool to the user for the sentence being translated after the receipt of a user's translation prefix input; and a pool update module configured to update the suggestion pool based on the user's input of a translation prefix.

Abstract: Methods and apparatus of automatically creating composite configuration items in a configuration management database are provided. A plurality of configuration items and a corresponding plurality of configuration item relationships are provided to the configuration management database. One or more composite configuration items are created from one or more of the plurality of configuration items in accordance with one or more types of the plurality of configuration items.

Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

Abstract: Embodiments of the present invention provide an approach for aggregating Internet addresses (e.g., Uniform Resource Locators (URLs)) in a networked computing environment. In a typical embodiment, a set of URLs is received (e.g., by a system/engine). Upon receipt, a composite URL comprising at least portions of each received URL is generated and associated with a newly generated web page. The received set of URLs are displayed on the web page in a list, or the like, that may be sorted according to a set of criteria.

Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract: CMOS devices (60, 61, 61?) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62?, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61?) are less likely to go into latch-up with increasing operating temperature.

Abstract: A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.

Abstract: A method achieves data consistency in a shared storage accessible by a first and second machine. The method includes, in response to receiving state information of the first machine, configuring the second machine to a mirrored operating state corresponding to an operating state of the first machine, receiving a notification that the first machine will overwrite existing data stored in the shared storage, and, in response to the notification, reading the existing data, storing a copy of existing data in a local storage of the second machine, and sending an acknowledgment to the first machine that the copy has been stored in the local storage, to enable the first machine to overwrite the existing data with newly written data. The method also includes, in response to receiving a failure notification, retrieving the copy of the existing data, overwriting the newly written data with the copy of the existing data.

Abstract: An approach is provided for communicating a media resource. The approach includes generating a widget information in response to a request by a user, associating the widget information with at least a portion of a media resource; encoding at least a portion of the media resource for a real-time exchange of communications, and transmitting at least a portion of the media resource and the widget information from one information handling system to another.

Abstract: Provided are techniques for analyzing fields. Statistical metrics for each field in a data set are received. A general interestingness index is generated for each field using one or more combination functions that aggregate standardized interestingness sub-indexes. One or more fields are identified as interesting for further analysis using the general interestingness index. One or more expert recommendations for field transformations are constructed for the identified one or more fields.

Abstract: Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

Abstract: Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.