Abstract: An error handling operation for checking of an array access in program code is modified during compilation thereof. A sequentially arranged null checking operation and array bounds checking operation for the array access are located. The array bounds checking operation has a corresponding error handling operation operable for setting an array bounds error. The located sequentially arranged null checking operation is removed. The corresponding error handling operation for the located sequentially arranged array bounds checking operation is modified to perform the removed null checking operation during execution of the program code.

Abstract: Disclosed is a service for displaying custom information. The service includes establishing a data connection to at least one data source, storing specific information via the data connection in the data source, and providing a data crawler to crawl said at least one data source using the stored information. The results are pushed from the data crawler to an end user for displaying a combination of the stored information and the at least one data source.

Abstract: A computer implemented method, a computer program product, and a data processing system trace information about current context and system state for either 32-bit or 64-bit applications. A 32-bit trace executable code and a 64-bit trace executable code are compiled for a trace script. A determination is then made as to whether an application process is a 32-bit process or a 64-bit process. Responsive to determining that the application process is the 32-bit process or the 64-bit process, an internal indicator is set to indicate the application process as either a 32-bit process or a 64-bit process. Subsequently, the internal indicator is identified as either indicating the 32-bit process or the 64-bit process. If the internal identifier indicates the application process is a 32-bit process, an instruction pointer is set to indicate the 32-bit trace executable code, and the 32-bit trace executable code is executed.

Abstract: Disclosed is a method of encoding JavaScript Object Notation (JSON) documents in an inverted index, wherein a tree representation of a JSON document is first generated, and, next, the JSON document is shredded into a list of <value, path, type, jdewey> tuples for each atom node, n, in the tree, where value is a label associated with n, path is a concatenation of node labels associated with ancestors of n, type is a description of a type of value, and jdewey of n is a partial Dewey code of its closest ancestor array node, if one exists, or empty, otherwise. Lastly, an inverted index is built using <path, type, value> as index term, and jdewey as payload. A method is also described to search the inverted index.

Abstract: Method, article of manufacture and apparatus for playing back recorded database activity in a graphical user interface. Chronologically ordered database event information is dynamically displayed in a user interface having user-selectable graphical elements associated with predefined playback controls.

Abstract: Systems and methods access non-compatible content repositories that are not natively accessible to a content management system. A metadata registry maintains metadata about content stored in both compatible and non-compatible repositories. For content in a non-compatible repository, the metadata indicates a repository interface capable of accessing the non-compatible repository. The content manager communicates with the repository interfaces to access the content in non-compatible repositories. The content manager may receive a request for content in a non-compatible repository, refer to the metadata registry to select a repository interface to employ, transmit a request for the requested content to the selected repository interface, and receive the requested content from the repository interface. A repository interface registry maintains information about available repository interfaces.

Abstract: The present invention involves implementation of an intelligent switching program, whereby the processing power required to monitor check-out stations is considerably reduced. The present invention monitors a subset of check-out stations at any given time, instead of monitoring all check-out stations at all times. The subset of check-out stations is determined dynamically according to, but not limited to, cashier records, input parameters from the user, current lane activity, past lane activity, time of day, etc. Statistical models (e.g., effective population sampling and/or population hypothesis tests) are developed along these lines that guide the lane selection process, whereby increases in the false-negative rate due to failure to monitor particular lanes when events of interest occur are controlled. By monitoring fewer check-out stations, while maintaining target performance accuracy, the amount of data that end users must deal with is significantly reduced.

Abstract: A method (and system) for coding a signal includes comparing a first prediction which is based upon a previously reconstructed signal to an actual signal to determine a first prediction error, comparing a second prediction which is based upon temporal filtering to the actual signal to determine a second prediction error, and selecting one of the first prediction error and the second prediction error.

Abstract: Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: A host reserves a device controlled by a controller that is coupled to the host. The controller starts a first timer, in response to a completion of input/output (I/O) operations on the device by the host, wherein the host continues to reserve the device after the completion of the I/O operations. The controller sends a notification to the host after an expiry of the first timer, wherein the notification requests the host to determine whether the device should continue to be reserved by the host. The controller starts a second timer, in response to receiving an acknowledgement from the host that the notification has been received by the host, wherein reservation status of the device reserved by the host is determined by the controller on or prior to an expiry of the second timer.

Abstract: Creating interoperability between a calling entity and an external service includes configuring an invocation channel using codeless process, designating the external service, passing source data from the calling entity to the invocation channel, the invocation channel formatting the data, invoking a connection to the external service, and passing the data over the connection to the external service.

Abstract: Embodiments can include instructions or steps, which when carried out, detect that copy operations are being performed on website data displayed to a user. Further to this detection, a co-browsing query for display to a user may be generated, an instruction to associate a co-browsing invitation with website data copied by the user may also be generated and a co-browsing invitation and pasted website data may be sent to an invitee.

Abstract: A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space.

Abstract: The present invention discloses an open contact center formed from multiple contact center components that conform to open standards and that intercommunicate utilizing open standards. The open contact center can provide automated interactive communications with callers, can provide queue management for callers waiting to communicate with live agents, can provide skills based routing for assigning live agents to callers based upon skills of the live agents and skills needed by the callers, and can provide tooling for provisioning and monitoring the live agents. In one configuration, the contact center components can execute within a middleware solution, such as WEBSPHERE, that has IP Multimedia Subsystem capability. Additionally, the contact center components can be implemented as service oriented architecture (SOA) components that communicate over an enterprise service bus (ESB).

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and d

Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: Embodiments of the invention provide a method for deploying and running an application on a massively parallel computer system, while minimizing the costs associated with latency, bandwidth, and limited memory resources. The executable code of a program may be divided into multiple code fragments and distributed to different compute nodes of a parallel computing system. During program execution, one compute node may fetch code fragments from other compute nodes as necessary.

Abstract: Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.