Abstract: A data processing system and method stores a relational database in which audit records are stored without compromising the ability to detect data tampering. The technique provides for detection of unauthorized row modification, row deletion, and row insertion. Extra measures are incorporated to protect from administrator attacks. In addition, the technique enables integrity checking and audit log archiving without having to suspend or bring down the audit subsystem. These on-line capabilities are especially important in mission critical applications which must satisfy the requirement that the application be disabled if the audit subsystem is not functioning properly.

Abstract: Various components are provided to manage a clustered environment. These components include a System Registry that provides a global data storage; a Configuration manager that stores data locally on nodes of the clustered environment and globally within the System Registry; a Liveness component to provide status of communications paths of the cluster; a Group Services component that provides services to one or more other components of the clustered environment; and a Resource Management component that communicates with one or more resource controllers of the clustered environment. Each of the components of the clustered environment has one or more data and/or functional dependencies on one or more other components of the environment. However, relationships between the components are created such that the data and functional dependencies form an acyclic graph (i.e., a cycle of dependency relationships is avoided).

Abstract: P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller.

Abstract: A system and method for converting 32 bit addresses into 64 bit addresses and enabling the 32 bit address to include a region index. The region index is stored in low order bits of the 32 bit address. In some architectures, namely the Intel IA-64 architecture, the low order bits are not used in entry point addresses because each entry point is on a 16 byte boundary. In the case of the IA-64 architecture, the low 4 bits of a 64 bit module entry point address are ignored. The region index in a 64 bit IA-64 address is stored in the high 3 bits of the address. Region index information is stored in the low order bits of the 32 bit address and copied to the high order bits for the corresponding 64 bit address. In this manner, the 32 bit address can include memory region index information without compromising the normal 4 gigabyte address space for a 32 bit address.

Abstract: A named range defined by a cell address range in a spreadsheet comprises a plurality of cells identified in each dimension by an address, each dimension comprising two directions. An open named range is specifyed to the named range in at least one open direction. A hidden named range with the cell address range of the open named range is expanded by one address in every direction specified as open. In response to user action, at least one direction is selected, the cell address range of the hidden named range is increased by inserting between two consecutive cell addresses, a new address in selected directions, the open named range is updated with the cell address range of the hidden named range shortened by one address in every direction specified as open.

Abstract: A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.

Abstract: A modified system causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64# signal low. This will synchronize reset and REQ64#, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.

Abstract: A method in an imaging system organizes and compresses into segments of limited size the image collection needed for the application of image based rendering to walkthroughs of large objects. For views from a limited range of positions only a corresponding limited segment of data needs to be transmitted, decompressed, and processed. A savings is thereby obtained in the startup time and memory required for execution of a walkthrough.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: Probes for electronic devices are described. The probe is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.

Abstract: A method and apparatus in a computer freeing space in a memory, wherein a plurality of objects are present within the memory. Responsive to an indication that space needs to be freed in the memory, an object is identified within the plurality of objects that is an oldest, least recently used object that is in use in the memory, wherein the object is an identified object and has a set of object attributes. The set of object attributes is inspected for the identified object to determine whether the identified object is a candidate for storage in a seldom used object store. Responsive to a determination that the identified object is a candidate, the object is copied to the seldom used object store, wherein the identified object becomes a relocated object. References to the relocated object to a location of the relocated object in the seldom used object store are adjusted. Space is freed in the memory occupied by the relocated object.

Abstract: A storage management system, apparatus, and method to increase the storage capacity of data storage media. Applicants' method uses a data storage device comprising a fixed device architecture, where that data storage device is capable of operating in a first capacity mode or in a second capacity mode, and where that data storage device is capable of switching between the first capacity mode and the second capacity mode. In certain embodiments, the first capacity mode utilizes a 22 bit blockid format and the second capacity mode utilizes a 32 bit blockid format. In other embodiments, the first capacity mode utilizes a 32 bit blockid format and the second capacity mode utilizes a 22 bit blockid format. A computer code product comprising a data management system which includes an operating system and data storage device microcode, which supports the capability to switch between alternative information storage architectures, and thereby, increase the capacity utilization of data storage media.

Abstract: A system and method for storing adapter card Option ROM BIOS extensions on the system's DASD and, more particularly, on a partition of the DASD that is generally inaccessible to the operating system. The system may partition the system DASD into a user partition and a hidden partition where the hidden partition is preferably inaccessible to the operating system. BIOS extensions files are stored in the hidden partition. The system BIOS, when executed, identifies the peripheral devices on the system and interrogates the hidden partition for BIOS extension files corresponding to each of the identified devices. If the hidden partition contains a BIOS extension file corresponding to an identified peripheral device, the file is verified for authenticity. If the verification completes successfully, the BIOS extension file is copied into shadow RAM and control is passed to it.

Abstract: A semi-conductor wafer test or burn-in apparatus having spring contacts made from a shape memory metal which plastically deforms under normal test loading and has a transition temperature at or above or at or below the burn-in temperature.

Abstract: The present invention is a method and system to minimize the timing errors introduced by the use of a sleep clock, utilized in timing a sleep period, for a mobile station. Further, the present invention restarts a high frequency reference clock after the sleep period with a zero mean time error to ensure that the receiver of the mobile station is properly synchronized with a base station for the receipt of pages. A low frequency sleep clock is calibrated with respect to a high frequency reference clock during a pre-defined calibration period. Based upon the calibration, a calibration error for the sleep clock is determined. Next, a wake-up time error is calculated, based upon the calibration error, to compensate for the error of the sleep clock. The wake-up time error compensates for the error of the sleep clock during the sleep period such that the reference clock restarts at the end of the sleep period with a zero mean time error.

Abstract: A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

Abstract: A smart filing system and method of use. The filing system includes a sanding or filing surface and a sensor for sensing the filed or sanded surface. An analyzing module analyzing the information obtained from the sensor and is capable of directing the system to modify the sanding. This modification may include changing the size of grains used for sanding or using a different sanding pattern and the like. A method for using the system is also provided.

Abstract: Disclosed is a method, system, and program for accessing a shared file system that is accessible to a first computer. The shared file system includes files in at least one file format compatible with at least one application program installed on the first computer. A request is received from an Internet browser program executing on a second computer for an applet over the Internet. The applet is transmitted to the browser program at the second computer. The applet is capable of executing in the browser program at the second computer to display a desktop interface at the second computer and establish a connection with the shared file system. The applet further provides access to at least one desktop application program through the desktop interface that is compatible with at least one application program installed on the first computer system. The desktop application program manipulates files in the same file format as the at least one application program installed on the first computer system.

Abstract: A method for providing customized information in a computer processing system includes the step of defining at least one rule for one of creating and retrieving at least one customized block of data. At least one customizable template is created which includes at least one reference to the at least one rule and at least one offset that specifies at least one position at which the at least one customized block is inserted into the at least one customizable template. The at least one customized block is inserted into the at least one customizable template at the at least one position specified by the at least one offset. The customized block, the customizable template, and/or the rule may be pre-stored in a cache of the computer processing system. The customized block may also be dynamically created.