Patents Assigned to International Business
  • Patent number: 6644974
    Abstract: A system and method for providing education that includes a database of educational material and a user interface. When prompted by a user through the user interface, the system provides a specific educational session from the database that is directed to satisfying a present business need/solution (e.g., a need for a specific legally binding written document with a customer or supplier). With the invention, the educational session produces a completed version of the legally binding written document. The user interface preferably includes a decision tree providing options for the user to select from different computerized educational sessions relating only to the present business need/solution. While the database includes educational material relating to many business needs/solutions, the decision tree limits user access to only those educational sessions relating to the present business need/solution.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Debra M. Adams, Dillon B. Edwards
  • Patent number: 6647513
    Abstract: An integrated circuit verification method and system are disclosed. The method includes generating a test description comprising a set of test cases. The functional coverage achieved by the test description is then determined. The functional coverage achieved is then compared against previously achieved functional coverage and the test description is modified prior to simulation if the test description achieves no incremental functional coverage. In one embodiment, generating the test description comprises generating a test specification and providing the test specification to a test generator suitable for generating the test description. In one embodiment, the test description comprises a generic test description and the generic test description is formatted according to a project specification and simulation environment requirements. If the coverage achieved by the test description satisfies the test specification.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventor: Amir Hekmatpour
  • Patent number: 6646285
    Abstract: The present invention provides a molecular device including a source region and a drain region, a molecular medium extending there between, and an electrically insulating layer between the source region, the drain region and the molecular medium. The molecular medium in the molecular device of present invention is a thin film having alternating monolayers of a metal—metal bonded complex monolayer and an organic monolayer.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Cherie R Kagan, Chun Lin
  • Patent number: 6647394
    Abstract: A method and system for providing multilevel information about aspects of business. The method comprises the steps of generating a display, on a computer display screen, of a tree having a plurality of nodes, and embedding in the nodes information about said business aspects. For example, trees may be generated that provide information about arranging, performing, monitoring, maintaining and controlling a business. Information may be embedded with a matrix approach. As examples, matrices may be used that provide information about business models, business expansion capabilities, business short and long term predictions, business competitor data, comparison and differences, business histograms and predictors, business responsible entities, division, product, entity business plans, reporting and results, and business alarm functions.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Louis Paul Herzberg, Charles Steven Lingafelt
  • Patent number: 6646544
    Abstract: An Address Compare Circuit (1) allows for a large compare function at high speed due to its unique self-timed evaluation clock and bit compare circuits. The address compare circuit can reliably self-time off of the input data which insures proper compare timing with respect to the arrival of two address busses being compared. The HIT evaluation clock is generated by a circuit that has additional control inputs to increase the arrival times of input data, resulting in a greater operating window. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventor: Antonio R. Pelella
  • Patent number: 6645867
    Abstract: Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Bruce B. Doris
  • Patent number: 6647536
    Abstract: A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as program “states” with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Douglas Hooker Bradley, Tai Anh Cao
  • Patent number: 6645789
    Abstract: An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Andres Bryant, Wayne J. Howell, William A. Klaasen, Wilbur D. Pricer, Anthony K. Stamper
  • Patent number: 6647515
    Abstract: A method and apparatus for determining common usage of elements among at least two channels in a data processing system having an arbitrary hardware element hierarchy including multiple channel paths over which data is transmitted. An internally executed initialization program builds a bit mask for channel paths to be compared wherein the bit masks describe the hierarchy of the hardware elements in the channel paths to be compared. A compare program provides a comparison result whose value reflects the impact of the failure of hardware elements that are common to the channel path being compared. The comparison results contains multiple bits, with set bits representing each element which is common to the hardware element common to the channel paths being compared. The impact of a failure of a common hardware element is greater the more significant the bit position of that component resides in the comparison results.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Eugene P. Hefferon, Hans-Helge Lehmann, William J. Rooney, Harry M. Yudenfriend
  • Patent number: 6647399
    Abstract: A system, method, program, and data structure for performing a backup operation of a target file. At least one operation is initiated to perform at least one delta backup of the target file to at least one delta backup set. A delta backup set includes changes made to a version of a full backup set of the target file generated at a first time, such as an incremental or differential backup operation. The at least one delta backup set is assigned a name component indicating the version of the full backup set generated at the first time subject to the delta backup and an operation is initiated to perform a full backup of the target file to a version of the full backup set at a second time. The second time follows the first time. A determination is made of all delta backup sets having the name component indicating the version of the full backup set generated at the first time during the full backup operation at the second time.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventor: Christopher Zaremba
  • Patent number: 6646996
    Abstract: To determine a network communications device type, (switch or router) without reference to internal information within the network communications device, two packets having preselected, differing sizes (e.g., 64 bytes and 1500 bytes) are sequentially transmitted from one network node to another through the network communications device. The difference between the transmission start times for the two packets, determined by time references set up based on internal data processing system high resolution counters and placed in the IP packet payload, and the difference between the receipt stop times—that is, when the last portions of the two packets are received—are compared. If the two differences are substantially the same, the network communications device is classified as a switch. If the two differences are unequal by an appreciable amount, the network communications device is classified as a router.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventor: Franck Barillaud
  • Patent number: 6644053
    Abstract: A refrigeration system for cooling a logic module includes an evaporator housing including an evaporator block in thermal communication with the logic module. The evaporator housing includes a humidity sensor for detecting a humidity within the evaporator housing. The system further comprises a controller for controlling a refrigeration unit supplying cold refrigerant to the evaporator block in response to the operating conditions of the logic module and the temperature of the evaporator block. In another aspect of the invention, two modular refrigeration units are independently operable to cool the evaporator block, and each refrigeration unit is controllable in various modes of operation including an enabled mode in which it is ready to cool the evaporator and an on mode in which it is actively cooling the evaporator. In another aspect of the invention, the evaporator block and a heater on a reverse side of the circuit board are particularly controlled during concurrent repair operations.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gary F. Goth, Jody A. Hickey, Daniel J. Kearney, Robert Makowicki
  • Patent number: 6646830
    Abstract: A multi-track magnetoresistive (MR) tape head with precisely-aligned read/write (R/W) track-pairs and a method for fabrication on a monolithic substrate wherein a plurality of tape heads are fabricated from a single substrate wafer by using complete thin-film processing on both sides of the wafer. The recording elements are aligned with readers opposite writers on the other side, providing a method for fabricating a multi-track thin-film magnetoresistive tape head with precisely-aligned R/W track-pairs fabricated on a monolithic substrate. As used herein, the term monolithic denominates an undivided seamless piece. The wafer is built using modified standard thin-film processes for fabricating direct access storage device (DASD) heads and modified substrate lapping procedures. The gap-to-gap separation within each R/W track-pair is reduced to nearly the thickness of the substrate wafer, which is significantly less than conventional separations known in the art.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Glenn Biskeborn, James Howard Eaton
  • Patent number: 6646607
    Abstract: A first antenna and a second antenna in first and second antenna-only areas of each face of an insulating substrate are arranged to decrease an antenna system having a plurality of antennas in size as the first antenna-only area and the second antenna-only area at least overlap with each other when viewed from a direction vertical to a face of the insulating substrate.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Hideyuki Usui, Takeshi Asano
  • Patent number: 6646250
    Abstract: A system and method for transferring information between spatially distinct points by modulating quantum states operatively coupling at least one transmitter and at least one receiver. In the preferred embodiment, fabrication of an elliptical quantum corral resonator on a length scale on the order of the electron wavelength enables the engineering of substantially confined quantum states as desired. A transmitter preferably located at a wavefunction antinode affects a modulation in the quantum states, and a receiver preferably located at a different wavefunction antinode detects the affected modulation in the spatially distributed quantum states. A second exemplary embodiment exploits the orthogonality of quantum wavefunctions to enable multiple channels of information to be transferred simultaneously through the same volume of space without crosstalk. Additional embodiments enable combinational processing of transferred information, which may be in any format, e.g.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Donald Mark Eigler, Christopher Paul Lutz, Harindran Chelvasekaran Manoharan
  • Patent number: 6644983
    Abstract: A contact assembly comprised of two parts bonded (e.g., welded) together, the first part including a male pin portion and the second part including a cylindrical jacket terminating in a flat end surface adapted for being electrically coupled (e.g., soldered) to a conductor (e.g., pad) on a substrate (e.g., PCB). Several contact assemblies may be positioned within a housing or substrate, to form a connector assembly which may then be positioned on and electrically coupled to a second substrate (e.g., a PCB), forming an electronic assembly.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Willi Recktenwald, Gerhard Ruehle, Rene Frank Schrottenholzer
  • Patent number: 6646355
    Abstract: A new interconnection scheme is disclosed for a tape automated bonding (TAB) package, a flip chip package and an active matrix liquid crystal display (AMLCD) panel, where an electrically conducting adhesive is used to form an electrical interconnection between an active electronic device and its components. The electrically conducting adhesive can be a mixture comprising a polymer resin, a no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating which provides a metallurgical bond between the conducting particles as well as to the substrates. The advantages of using the electrically conducting adhesives include reduction in bonding pressure and/or bonding temperature, control of interfacial reactions, promotion of stable metallurgical bonds, enhanced reliability of the joints, and others.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Sung Kwon Kang, Sampath Purushothaman
  • Patent number: 6644773
    Abstract: Provided are a method, system, and an article of manufacture for registration calibration of a printer. An application prints reticle patterns on a printed page. An imaging device creates a digital image of the printed reticle patterns. If color registration on the printer is improper, the digital image exhibits interference patterns. The application compares the interference patterns to the reticle patterns, and based on the results of the comparison adjusts the color registration of the printer.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Carl Robert Bildstein, Jennifer Quirin Trelewicz, Joan LaVerne Mitchell, Arthur Kenneth Ford, Michael Thomas Brady
  • Patent number: 6646345
    Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
  • Patent number: 6645796
    Abstract: A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, John Edward Sheets, II