Abstract: A semiconductor device includes a field-effect transistor (FET), and a fuse which includes a graphene layer and is electrically connected to the FET.

Abstract: Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.

Abstract: A method and apparatus is provided to discover and integrate applications in an application router framework. The discovery operation includes receiving a registration notification for an application on a network, adding information describing the application to a repository into a data structure and publishing the data structure onto an application router. The association operations include querying one or more application routers on an application network for meta-data and other information on applications, exchanging the meta-data and other information between the application routers and associating the applications together automatically using their respective application protocols.

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.