Abstract: An adaptive output driver includes circuitry for sensing the capacitive loading of a driver circuit and then adjusting the drive output so that the output signal possess a desired slew rate. In one embodiment, the circuit of the present invention includes a capacitance sensor, a control circuit, and an output driver. The capacitance sensor measures the unknown load capacitance. The control circuit generates a control signal in response to the capacitive load measurement. The output driver receives the control signal and in response produces an output level which when supplied to the capacitive load produces an output signal having the desired slew rate.

Abstract: An activity sensor monitors a microprocessor based system for a change in a logic state. In response to the change, the activity sensor provides a reset timer pulse to a delay timer circuit. The delay timer is a counter that stores a signal representation of the number of timing pulses provided by a timing clock. In response to the timer reset signal, the delay timer is reset. When the timer reset pulse is not provided for a predetermined interval, the delay timer generates a timeout pulse that causes a reduction in the frequency of a system clock.

Abstract: A current-controlled output buffer circuit includes a control circuit, a charging circuit, and a discharging circuit. The control circuit is configured to receive a control signal, and in response produces a charging signal and a discharging signal. The charging circuit is configured to receive the charging signal and in response, supplies a charging current to an output terminal, the magnitude of said charging current producing a signal rise time. The discharging circuit is configured to receive the discharging signal and in response, sinks a discharging current from the output terminal, the magnitude of the discharging current producing a signal fall time.

Abstract: An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode to accomplish required system functions with a reduced overall pin count.

Abstract: An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.

Abstract: A discriminator provides an output signal having an amplitude proportional to the frequency of a measured signal. The output of the discriminator is connected to a differentiator circuit that provides an impulse signal proportional to a cycle to cycle frequency change of the measured signal.

Abstract: Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

Abstract: A flexible, symmetrical, MOS integrated circuit structure and layout employing a unit cell approach for customized wiring. Special features include multiple contacts on individual source/drain elements, rectilinear interconnections in the X- and Y- directions, and interconnection underpasses integral with the source and drain regions of the individual devices. The structure is especially applicable to complementary MOS integrated circuits of large complexity.