Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: An apparatus is described that is used to load containers with small objects similar to Flash memory SD or micro SD cards. The apparatus can be made in three configurations; a fully manual operated configuration, a manual configuration in combination with one or more automated machines, and finally as a fully automated handling apparatus. In its simplest form, the apparatus consists of a base plate with an attached bar containing a grooved bar member such that the jewel cases are restrained in the grooved bar member in such a way as to allow the jewel cases to be moved in a linear or circular direction and provide means such that the cases can be easily loaded with the objects and then removed from the base plate.

Abstract: A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral.

Abstract: A universal memory bus coupled between a system's CPU and the system memory is composed of four channels; a primary channel, an identification channel, a programming channel and an expansion channel. The primary channel communicates operating system data necessary to boot the system. The identification channel communicates signals describing the device composition of the system memory. The programming channel communicates programming signals to all of the programmable memory devices within the system memory and thus allows complete programmability of those devices. The expansion channel provides data and programming access to a memory device subsequently added to the system memory.