Patents Assigned to INTERNATIONAL SEMATECH
  • Publication number: 20130105910
    Abstract: Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 2, 2013
    Applicant: International SEMATECH
    Inventor: Intermational SEMATECH
  • Publication number: 20100320510
    Abstract: A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.
    Type: Application
    Filed: June 21, 2009
    Publication date: December 23, 2010
    Applicant: INTERNATIONAL SEMATECH
    Inventors: Wei-Yip Loh, Prashant Majhi, Brian Coss