Abstract: A thin flexible multi-layered printed circuit cable manufactured by a relatively simple process and having improved electro-magnetic interference and impedance characteristics is described. The cable includes: an insulating substrate layer; a wiring layer formed on the insulated substrate layer; a coating layer laminated on the wiring layer; a first non-woven metal fiber layer laminated on the coating layer; and a second non-woven metal fiber layer laminated on an opposite surface of the substrate layer. Because the cable is coated with a conductive non-woven or woven metal fabric, electromagnetic waves generated during transmission of high speed data are fully shielded. The non-woven or woven fabric having a wide surface area, is soft and can make good surface-to-surface contact.

Abstract: A one step method for curing encapsulant and joining Ball Grid Array (BGA) solder balls comprises curing an encapsulant material simultaneously with the joining of the eutectic material of the apparatus whether that eutectic material is a solder paste or preform, the balls being of a higher melt material or the balls themselves being an eutectic material. The method performs both functions in one pass through a furnace avoiding the separate and time consuming encapsulant and/or underfill curing step.

Abstract: An interconnect substrate structure for electrical interconnection between two electronic modules having differing conductive array parameters. The interconnect structure comprises an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer, with the conductors comprising a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection.

Abstract: A precise volume, precisely registerable carrier is provided for use with injection molding for producing integrated circuit bump contacts in the “flip chip” technology. A hemispherical cavity is produced by etching through and undercutting a registered opening into a transparent carrier. The hemispherical cavity has related specific volume and visible peripheral shape that permits simple optical quality control when the injection molding operation has filled the cavity and simple optical registration for fusing to the pads on the integrated circuit.

Abstract: A method and apparatus for decrypting an input block encrypted under a predetermined key in a cryptographic system having a cryptographic facility providing cryptographic functions for transforming blocks of data. The cryptographic functions include an encryption function for encrypting a block under a predetermined key and a transformation function for transforming a block encrypted under a first key to the same block encrypted under a second key. The cryptographic functions have at least one key pair with the property that successive encryption of a block under the keys of the pair regenerates the block in clear form. The input block is first transformed into an intermediate block encrypted under one of the key pair using the transformation function. The intermediate block is then further encrypted under the other of the key pair using the encryption function to generate an output block successively encrypted under the keys of pair, thereby to regenerate the input block in clear form.

Abstract: A viable T-gate FET is produced even when the cap of the “T” is mis-aligned from the stem of the “T”. A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avoid the etching away of portions of the stem if the cap is mis-aligned relative to the stem. To that end, germanium (Ge) may be used as the material for the cap of the T-gate and poly silicon (polySi) may be used as the material for the stem of the T-gate. Since germanium can be etched selectively relative to silicon from 10:1 to as much as 20:1, the cap of the T can be formed without appreciable damage to the stem portion and thus without damage to the resultant FET device.

Abstract: A test fixture is described which includes a camming assembly for eliminating misalignments in the probe testing of electronic card assemblies. The test fixture provides a pair of cams oppositely situated from the probes of a Side Access Unit (SAU). These cams are pneumatically actuated slightly prior to, or instantaneously with, the SAU. The actuation of the cams provides a mechanical stop with zero tolerance, so that the misalignment of test pads and probes, caused by the forward movement of the test probes, is eliminated.

Abstract: A data processing system and method are described for remotely accessing a client computer system's individual initialization settings. The client computer system is coupled to a server computer system to form a local area network. The server computer system transmits a command to the client computer system to access a selected one of the client computer system's initialization settings. In response to a receipt of this command by the client computer system, the client computer system accesses only selected ones of the initialization settings. The client computer system may be powered off while the initialization setting is accessed.

Abstract: A planarized interleaved capacitor for use with a substrate. The capacitor has a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.

Abstract: A book-like fixture and method for assembly of a plurality of multi-layered ceramic packages including a substrate and a cap. The fixture has a baseplate, a removable tray, an alignment plate for precisely aligning the caps with the substrates, a compression plate, and a plurality of compression devices designed to uniformly distribute compressive force on the plurality of packages. The fixture is preferably adapted for use of removable trays conforming to the Joint Electronics Design Engineering Council Tray Standard. The compression devices preferably have a spring, preferably a detachable leaf spring, and a compression plate placed over each cap. The structure of the fixture allows replacement of the springs and other modifications to allow assembly of multi-layered ceramic packages of differing dimensions. The structure of the fixture also allows stacking one on top of another.

Abstract: A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.

Abstract: A method of forming the device, includes selective area deposition of a ferromagnetic material on a substrate. The substrate surface is partially covered with material having a crystal structure having at least one symmetry relation with the crystal structure of the ferromagnetic material.

Abstract: A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method for migrating legacy applications into a new software product architecture using a functional conversion module located within a system controller. The functional conversion module comprises a migration plan shut off. The functional conversion module further comprises three paths or branches through which a functional request can be routed. Functional requests which are not identified in the migration plan are routed through the first path and the functional request is sent to the pre-existing software and executed as requested. Functional requests identified in the migration plan for which the pre-existing software is in control are routed through the second path, and the functional request is sent to the pre-existing software and executed as received. In the background, the functional request is translated for the new software and sent to the new software and executed.

Abstract: A method of fabricating a semiconductor device comprising: forming a trench on the face of a silicon substrate of a first conductivity type; depositing a conformal silicon layer of a second conductivity type into the trench; etching away the silicon layer of a second conductivity type selectively to leave portions of the silicon layer in the trench; annealing to drive dopant from the portions of the silicon layer through the walls of the trench into adjacent areas of the silicon substrate; and forming a gate structure in the trench, and source and drain diffusion regions in said silicon substrate on opposing sides of said gate structure.

Abstract: An electrically activated fuse with a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates bringing the fusible link to its melting point. Fuse dimensions (width and length) are each between 0.1 and 2.0 microns, with a thermal mass of the heater element being sufficient to melt the fusible link.

Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Abstract: A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

Abstract: A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.