Abstract: A method and apparatus for testing or verifying proper operation of a data output system of a memory system are provided. A known data signal is applied to a bit line, independent of the memory cells of the memory system associated with the bit line. Expected outputs of the data output system are determined based upon the formation or configuration of the data output system and the known data signal. Following application of the known data signal to the bit line, actual outputs of the data output system are compared to the expected outputs to verify proper operation of the data output system.

Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon.

Abstract: A voltage regulator circuit that minimizes the bias current flowing between a first voltage terminal and a second voltage terminal. The circuit receives input signals via a first and a second input terminal, and provides an output signal via an output terminal. The circuit includes a differential input stage, an output stage, a first sub-circuit for reducing the current flowing through the output stage between the first voltage terminal and the output terminal, and a second sub-circuit for reducing the current flowing through the output stage between the output terminal and the second input terminal. An alternative embodiment combines the power reduction circuitry with additional circuitry decoupling the input and output stages to provide enhanced design flexibility.

Abstract: Accordingly, a computer implemented method, uniquely programmed computer system, and article of manufacture embodying computer readable program means all allow a customer on an external network to initiate an authorized business transaction utilizing internal business resources on an internal network without violating security firewalls. Specifically, the method directs an internal computer system to allow an external computer system to initiate a transaction request using internal resources without violating a security firewall between the internal computer system and the external computer system. The method includes a first step of authenticating a connection initiated by the internal computer system between the internal computer system and the external computer system, thereby establishing an authenticated connection. The second step includes calling by the external computer system a transaction request received by the external computer system.

Abstract: Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned a location without determining an allowable physical location on the integrated circuit, and all timing calculations are based on the assigned location. Then, once the timing constraints have been met by one or more new circuit elements, an incremental layout is performed to find physical locations for the new circuit elements, using the assigned locations as initial targets. By using assigned locations during timing calculations and later determining valid physical locations, many different circuit configurations may be evaluated in a short period of time, with only the best ones going through the more time-consuming step of layout and routing.

Abstract: An image processing and retrieval system in which images are captured and stored at the remote site where the document processor is located which codelines from the documents are captured and transmitted to a central host computer site, whereby the accounting and financial records may be done at the host computer at the central site and image statements and other image processing activity to process the image may be done at remote sites.

Abstract: A method and computer program product are provided for implementing a stable integral equation model for both the time and frequency domains. The stabilization method of the invention is applicable to electric field integral equation (EFIE) formulations, to magnetic field integral equation (MFIE) formulations, and to combined field integral equation (CFIE) formulations. For example, an EFIE formulation can be used in the circuit domain called partial element equivalent circuit (PEEC). Each volume cell is subdivided into a finite number of partitions. A partial inductance term is calculated consisting of a summation over all the finite number of partitions in each cell. Each surface cell is subdivided into a finite number of subcells. A coefficient of potential term is calculated consisting of a summation over all the finite number of subcells in each surface cell. Both the partial inductances and the coefficients of potential are calculated without increasing the number of unknowns.

Abstract: An electronic package (400), particularly a BGA, including a circuitized substrate (120) and one or more active devices (110) attached thereon by means of corresponding conductive pads provided on a surface of the substrate (120); each conductive pad is splitted in a plurality of parts (212-218) not in contact. Such parts (212-218) may be separated by a wireable area of the substrate (120), thereby providing one or more wiring channels. In addition, the same parts (212-218) may be connected in interfacing couples at different electrical potentials (ground and power) and decoupled to each other by means of capacitors (410); the connections to the ground and power are achieved by metallized holes provided through the substrate (120).

Abstract: AS/400 POP3/MIME clients that are making use of the POP3 server support move mail through a SNADS network to other POP3 clients. The messages sent between these clients make use of an existing SNADS network without having to resort to converting or mapping or breaking apart an ASCII SMTP/MIME text message to an equivalent OfficeVision/400 format. Likewise, non-text SMTP/MIME messages or attachments sent this way do not need to be mapped to OfficeVision/400 PC file objects. This is accomplished by encapsulating the SMTP/MIME message in an AS/400 Object Distribution as a specific database object. Once encapsulated, the SMTP/MIME message is an object distribution message as far as any reference to that message made by any SNADS function anywhere in the SNADS network.

Abstract: A credit-based flow control checking scheme is presented for controlling data communications in a closed loop system comprising a sender, a receiver and a link coupling the sender and receiver. The credit-based scheme includes automatically periodically transmitting a credit query from the receiver to the sender and upon return receipt of a credit acknowledge containing the available credit count maintained by the sender, determining whether credit gain or credit loss has occurred subsequent to initialization of the closed loop system. Along with automatically determining whether credit gain or credit loss has occurred, a method/system is presented for automatically correcting the loss or gain without requiring resetting of the closed loop system.

Abstract: An automated programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a means for automatically controlling the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by the automatic control means. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The control means also includes an update code for updating the firmware in a selected memory. The automated store further includes means for allowing the computer system to recover automatically from invalid firmware stored in one of the memories.

Abstract: A method for partitioning keys onto radix tree logical pages and a parallel index page build algorithm in order to provide radix tree build speedup proportional to the number of processors on the system and controlled efficient page utilization. Also, since keys are intelligently partitioned so that a complete set of keys is inserted into a logical page, there is no page overflow during the tree construction and thus page splitting is eliminated. Since radix index trees are really groups of logical pages in which each logical page contains a small tree, the tree is built (with respect to the logical pages) from the bottom up, while within each individual logical page the tree is constructed from the top down. The space required for a logical page is pre-allocated to allow construction of limbs to begin without waiting for the build of their underlying pages to complete.

Abstract: A wavelength division multiplexer (WDM) unit (12) includes a plurality of Input/Output cards (IOCs 14). Each IOC is bidirectionally coupled to I/O specific media (fiber or copper) and to two coaxial cables. Also bidirectionally coupled to the coaxial cables are a plurality of Laser/Receiver Cards (LRC 20). The interface between the IOCs and the LRCs is an Emitter Coupled Logic (ECL) electrical interface that is conveyed over the coaxial cables. Each LRC is bidirectionally coupled by two single mode fibers to an optical multiplexer and demultiplexer, embodied within a grating (24). An input/output port of the grating is coupled to a fiber link (28) that enables bidirectional, full duplex data communications with a second WDM. Each WDM also includes a Diagnostic Processor Card (DPC 28) that receives status signals from the IOCs and LRCs, that forwards the status signals on to an external processor, and which generates control information for the IOCs and LRCs.

Abstract: A printer has a control circuit to stop a print head from printing when paper runs out or when the cover of the printer is opened is disclosed. Only one switch is used to detect the absence of paper and the position of the cover.

Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer.

Abstract: An apparatus, system and method are described for generating a continuous and linear position signal generated from stitched position error signal (PES) components, for use by a servo control system in positioning a transducer with respect to a storage surface. Continuity is achieved by providing a normalization stage in the servo control loop for correcting discontinuities at the stitch points with minimal impact to the PES zero-crossing points. According to a first preferred embodiment normalization is applied using an algorithm determined by the width of the read transducer. According to a second preferred embodiment, normalization is selectively applied near the stitch points of the PES components, but is not applied at their zero-crossing points. In another preferred embodiment, a first normalization algorithm is applied near the stitch points, and a second normalization algorithm is applied at the zero-crossing points.

Abstract: A product created through the reflow of low melting point solder on select contacts of a printed circuit board. In one form, the printed circuit board has fine pitch devices, including flip-chip integrated circuits, connected to a board having conventional coarse pitch surface. The fine pitch contacts of the board are exposed through holes in a stencil characterized in its ability to withstand solder reflow temperatures, not be wettable by solder, and have a coefficient of thermal expansion relatively matching the printed circuit board. Low temperature solder paste is screen deposited into the stencil openings. With the stencil fixedly positioned on the board, the solder paste retained by the stencil pattern is reflowed to selectively form on the underlying contacts of the printed circuit board. Thereafter, the stencil is removed from the board and the board is subject to previously practiced depositions of flux and paste in preparation for fine and coarse pitch component placement and ensuing solder reflow.

Abstract: A read sensor includes first and second substantially planar magnetoresistive spin valves, parallel to each other. Each spin valve includes a pair of ferromagnetic layers. Between the spin valves lies a bias conductor, separated from each spin valve by respective insulating layers. In each spin valve, the outer ferromagnetic layer is a current-induced ferromagnetic pinned layer whose magnetization direction is pinned by a pinning field supplied by a bias current flowing in the bias conductor. Sense currents are directed through the spin valves in a direction substantially perpendicular to the magnetization directions of the current-induced ferromagnetic pinned layers. The magnetization orientations of the ferromagnetic layers are established by a combined field provided by the sense and bias currents. When the read sensor detects an external magnetic field, each spin valve exhibits a voltage drop.

Abstract: A method and apparatus for converting and displaying at a client workstation a multimedia mail message. The mail message contains textual material and non-text embedded material. The method includes the steps of converting the mail message into text and non-text portions, storing the non-text portions in non-text files; and displaying a converted message. The converted message includes the text portion in clear text, and references to the non-text files.

Abstract: A composite containing an integrated circuit chip having conductive site thereon and electrically conductive leads that are interconnected to the conductive site by electrically conductive wire; wherein the wire is coated with a dielectric material. Also, a method for fabricating the composite is provided.