Abstract: Methods and systems for detecting block based video dropouts in one or more fields associated with various video frames is provided. A current field is divided into a plurality of blocks. A set of activity blocks is identified from the plurality of blocks. The activity blocks are then processed to identify horizontal and vertical lines which are then further processed to form one or more candidate error blocks. The candidate error blocks are validated for start and end to determine a count of video dropout errors associated with the current field.

Abstract: Systems and methods for detecting chroma dropout errors in one or more fields associated with various video frames are provided. Pixels associated with a current field are divided into a set of pixel pairs. Co-occurrences matrices are calculated for previous and subsequent fields. A first pixel pair associated with the current field is selected. First and second set of entries are selected from the co-occurrence matrices corresponding to the previous and subsequent fields. The first pixel pair is searched in the first and second set of entries. An absence of the first pixel pair in the first and second set of entries satisfies a first criterion of chroma dropout error. Other criteria in addition to the first criterion are evaluated to label the first pixel pair as erroneous.

Abstract: A system and method for the identification and analysis of cadence pattern is disclosed. The method uses previous and current fields to generate the difference between the field values. The difference of these values along with the field relations is passed to the state machine to generate the state of the top and bottom fields. Based on the top and bottom state the cadence signature is generated and by using the Fourier analysis the principle frequency of repeated cadence pattern signature sequence is identified. Each of the cadence signatures present in the cadence pattern signature sequence is decoded to calculate the pull-down value of the cadence pattern. The pull down value then gives the actual cadence pattern.

Abstract: The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CMmax). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.

Abstract: The invention provides a method, system and computer program product for detecting field order of a video sequence. The method includes processing a top and bottom field picture of a first frame and a second frame, in which the first and second frames are consecutive frames of a video sequence. Difference frames are obtained by calculating the difference of the top and bottom field pictures of the first and second frames. Thereafter, field order is detected using the difference frames.

Abstract: A method and system for calculating a blur artifact in a video are disclosed. The video includes a series of frames captured at a predefined interval of time. The frames include one or more pixels. Calculating the blur artifact in the video includes identifying a focused area in a set of frames. Further, edges are detected in each of the frames. Furthermore, the blur artifact is calculated as a ratio of number of blurred pixels and total number edge pixels.

Abstract: A method and system for detecting and quantifying blockiness in a video file is disclosed. The video file is a file that has been decompressed by using standard DCT algorithms. The method includes segmenting each frame of the video file into multiple blocks. The method also involves comparing the intensity gradients of each block with one or more threshold values. The one or more threshold values represent predefined intensity variation characteristics. Further, the method includes determining the intensity variation parameters of each block, based on the comparison. Thereafter, a blockiness index is calculated for each block, after which a blockiness value is calculated for each frame. Finally, a blockiness level is assigned to each frame, based on its blockiness value. The blockiness level is a comparative measure of the blockiness of a frame that represents the blockiness content in the frame.

Abstract: A method and system for calculating an interlace artifact in image data are disclosed. A motion picture of the image data comprises a series of frames, captured at a predefined interval of time. During processing of the motion picture, the frames are divided into fields, each field comprising one or more pixels. A difference between the pixels of the fields is calculated. Thereafter, edges of the pixels are calculated in the fields. The method and system then identify the focused area in the fields. To calculate the interlace artifact in the motion picture, the displacement of the focused area is calculated by using motion vectors. The artifacts are calculated as a ratio of a number of pixels based on motion vector calculation.

Abstract: A method for automatically verifying one or more features of file-based media content (108) is disclosed. This file-based media content includes one or more media content files. The method includes customizing (204) a test plan on the basis of the one or more features. Customizing the test plan includes creating, modifying or utilizing at least one media content check of one or more media content checks. A media content check verifies at least one feature of the one or more features of the file-based media content. Further, the method includes verifying (206) the one or more features, based on the customized test plan. The method also includes documenting (208) the results obtained from the verification of the one or more features.

Abstract: A method and a system for characterizing an integrated circuit (IC) design are disclosed. The method includes receiving a description of leaf cells used in the IC design. The IC design is described in a high-level language by using the description of the leaf cells. The description of the IC design includes specifying placement of the leaf cells and specifying connectivity between them. Further, the method includes extracting a circuit netlist file based on the physical layout of the IC design. The instructions are defined in the high-level language to perform simulations on the extracted circuit netlist file. These simulations are performed on the circuit netlist file to determine the values of the design parameters. Furthermore, the method includes providing the values of the design parameters of the IC design in a pre-defined output format based on the simulations.

Abstract: A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or an output load, or both, corresponding to the functional module. Further still, the method includes calculating (108) size of a plurality of transistors in the functional module. The system includes a characteristic table generator (302) and an optimizer unit (304). The characteristic table generator (302) generates the characteristic table. The optimizer unit (304) selects the functional module from the one or more functional modules. The optimizer unit (302) further resizes the plurality of transistors in the functional module.