Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: Disclosed are full-bridge power converters providing DC output power at increased conversion efficiencies, and methods of operating full-bridge power converters providing DC output power at increased conversion efficiencies. In disclosed embodiments, the switches of the full-bridge are operated to reduce conduction losses and to provide for zero-voltage switching.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract: A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Abstract: A circuit for setting a reference voltage in a floating gate circuit is configured as a precise voltage comparator circuit with a built-in programmable voltage reference. Once the one or more floating gates in the floating gate circuit are set during the a SET operation, the floating gate circuit is configured during a READ mode as a comparator circuit with a built-in voltage reference.

Abstract: A voltage regulator includes a voltage source for providing an input voltage and circuitry for regulating the input voltage to provide an output voltage. The circuitry for regulating the input voltage includes at least a high side switch and a low side switch. A skip mode controller controls the high side switch and the low side switch in order to minimize conduction losses and switching losses within the voltage regulator.

Abstract: A multiphase DC-to-DC converter includes at least two phase circuits each having upper and lower power switches and a front-end inductor that is operative for forming a resonant tank circuit with the phase circuits to ensure zero voltage switching and minimizing power losses.

Abstract: A transmitter for a digital transmission signal includes a pre-distorter to improve linearity of a power amplifier. An amplified transmission signal is conditioned into a narrowband feedback signal that is responsive to a logarithm of the power appearing in out-of-band components of the amplified transmission signal. The feedback signal is processed in a pre-distortion processor that implements a genetic algorithm to adapt pre-distortion functions implemented in the pre-distorter and improve linearity over time. The genetic algorithm tests a population of randomly-generated pre-distortion functions for fitness. A baseline component of the coefficients from pre-distortion functions used in a subsequent population tracks the best-fit pre-distortion function from the current population, allowing the use of a limited search space. New populations are generated from old populations using an elitism process, and randomized crossover, and mutation processes.

Abstract: A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.

Abstract: A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities.

Abstract: A power monitor circuit and method delays the start of a computer until multiple power lines are at a safe level of operation. The integrated circuit monitors only the voltage of a primary power supply output and eliminates the need for monitor circuits on each supply output. The power supply is made to exacting specifications that tie the 5 volt and 3.3 volt supplies to the primary 12 volt supply. The ATX power supply drives the 3.3 and 5.0 supplies to reach 90% of their values within 40 ms after the 12 volt supply reaches 90% of its value. A time delay circuit 25 delays switching the 3.3 and 5 volt dual outputs from the standby voltage supply to the active voltage supplies until after the primary 3.3 and 5 volt are at a safe operating level.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: A controllably switched arrangement selectively couples multiple circuit functions, such as reverse polarity detection, ring-trip and line voltage measurement, of a telecommunication card to the same external programming component (e.g., capacitor) on an as needed basis, by means of associated coupling circuits and a controlled switching circuit. The coupling circuits are controllably enabled/disabled in association with the particular circuit function required, while the controlled switching circuit selectively connects each coupling circuit with the external component. Through combined control of the coupling circuits and the switching circuit, respectively different circuit functions can be implemented with the same external component.

Abstract: A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.