Abstract: A system for tracking high-dynamic targets by relaying semi-processed GPS signals to a remote signal processing station with a relatively small and efficient bandwidth is described. Such processed GPS signals can be provided in a high-dynamic environment without the assistance of an inertial measurement unit (IMU). One embodiment includes a hybrid translator that is a hybrid between a full GPS navigation system and a translator system. The modulated GPS signals, such as modulated C/A codes, are pre-processed to reduce the amount of information required to reconstruct the GPS signal received by the hybrid translator. For example, the GPS signals can be processed to a pseudo-range measurement and an indication of an amount of corruption of delta range in the pseudo-range measurement, which are then provided to signal processing at a remote location, such as at a ground station, via a wireless downlink.

Abstract: A multi-pass frequency hop timing acquisition correlator that produces a more accurate time estimate from the fast acquisition frequency hop signal is disclosed. The time estimate produced by the multi-pass acquisition correlator is more accurate than the ¼ hop estimate produced by single-pass fast acquisition correlators. The multi-pass frequency hop timing acquisition correlator uses a time estimate generated by a previous pass through the multi-pass frequency hop timing acquisition correlator as a starting point for computing a new, more accurate, time estimate. Thus, the second pass through the multi-pass frequency hop timing acquisition correlator produces a time estimate that is relatively more accurate than the time estimate produced by the first pass. The more accurate time estimate produced by the multi-pass acquisition correlator reduces the hardware and time needed by the direct acquisition process to acquire the M-code.

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory. One receiver includes a Doppler offset generator that can advantageously offset a time index used to address a tap position in a non-coherent memory to compensate for code drift in a code with a frequency offset. The amount of offset is computed by accumulating clock cycles of a clock signal that is related to the frequency offset computed by the DFT or FFT frequency bin. The offset aligns a correlation peak in the received code such that the correlation peak can be accumulated in relatively fewer tap positions or addresses.

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous detection of multiple frequencies allows the receiver to search the frequency range of the transmitted signal in larger increments of frequency, thereby increasing the speed of acquisition. One receiver does not use coherent integration before computation of the transform and advantageously maintains a flat frequency response. The flat frequency response of the DFT circuit enables searching of multiple frequency offsets without CPU intensive processing to compensate for frequency response variations. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory.

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous detection of multiple frequencies allows the receiver to search the frequency range of the transmitted signal in larger increments of frequency, thereby increasing the speed of acquisition. One receiver does not use coherent integration before computation of the transform and advantageously maintains a flat frequency response. The flat frequency response of the DFT circuit enables searching of multiple frequency offsets without CPU intensive processing to compensate for frequency response variations. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory.

Abstract: An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The method applies a sequential test algorithm to the detection of a correlation signal. The method allows the receiver to search a range of frequency-time space relatively quickly.

Abstract: A GPS system and method for real-time determination of integer ambiguities in a global positioning system (GPS) receiver and, more specifically, to a GPS system and method for determining integer ambiguities of a GPS solution using a Kalman filter with double difference integer ambiguities as additional states to estimate the ambiguities until they are estimated to within a sufficiently tight variance around their error estimates. Thereafter, all the candidate integer ambiguity values are searched in the range domain, e.g., along the double difference lines-of-sight for each satellite, until one is selected; if the after-the-fit residuals for the selected integers are below a certain threshold, then the selected integers are accepted as the integer ambiguities. If not, another set of candidate integer values are selected and analyzed.

Abstract: A backlighting unit for illuminating a planar display is provided, comprising an illumination source having a light emitting portion for emitting illumination toward the generally planar display, and a reflector for collecting the emitted illumination and reflecting the collected illumination toward the planar display, the reflector being positioned intermediate the illumination source and the display. The illumination source is a fluorescent lamp having an interior surface thereof substantially coated with a phosphor, and the light emitting portion is an aperture in the fluorescent lamp wherein no phosphor coating is present. The fluorescent lamp may be provided with a reflective wrap for increasing its illumination gain. A lens positioned between the reflector and the display receives the illumination reflected by the reflector and redirects the received illumination toward the display to provide even backlit illumination thereof.

Abstract: A digital downconverter circuit for a digital data transmission system is provided, comprising (i) a bandpass filter circuit for filtering a received analog intermediate frequency (IF) carrier signal onto which baseband information has been modulated, and outputting a bandpass analog IF signal; (ii) an analog-to-digital converter for converting the bandpass analog IF signal into a bandpass digital IF signal; (iii) a phase shifter device for outputting a complex pair of phase shifted baseband signals operating at a local baseband frequency; (iv) a mixer device for mixing the bandpass digital IF signal separately with each of the complex pair of phase shifted baseband signals and outputting a complex combined baseband/bandpass signal comprising inphase and quadrature components; (v) filtering circuitry for recovering the baseband information onto the phase shifted baseband signals; and (vi) sampling circuitry for sampling the information-bearing recovered baseband signals and outputting a sampled complex baseba

Abstract: A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs.

Abstract: A backlight comprising a serpentine fluorescent tube nested in a uniquely shaped reflector. Much of the light emitted from the tube is directly emitted to a bounded image plane. The reflector reflects a substantial portion of the rest of the light emitted by the tube to the image plane in such a manner that a very bright and uniform image is formed at the image plane.

Abstract: A multiple bandpass filter is disclosed having a common input intercoupling a plurality of parallel single bandpass filters which are further intercoupled to provide a composite signal at a common output. The multiple bandpass filter of the present invention is appropriate for application to ceramic filters. In a preferred embodiment, the multiple bandpass filter of the present invention has a common input, parallel distributed resonator single bandpass filters, and a common output, all integral to the same ceramic structure. The multiple bandpass filter comprises a ceramic block having a plurality of rows of holes extending from the top of the bottom of the block and a slot extending from the top to the bottom of the block, separating the rows. The block and interior of the holes and slot are substantially covered with conductive material. An area near one end of each of the holes is bare ceramic.

Abstract: A numerically controlled oscillator includes a number of N-bit adders that perform parallel addition of a frequency setting word to an accumulated output. A first adder adds the frequency setting word to the accumulated output. A second adder adds a multiple of the frequency setting word to the accumulated output. Additional adders may be included to add other multiples of the frequency setting word to the accumulated output. The sum output of the adder in which the highest multiple of the frequency setting word is added is saved as the new accumulated output. The outputs of all the adders are saved and are mutliplexed out in sequence at a predetermined clock rate as a series of input values to a sine lookup table in a ROM. The outputs from the ROM form the digitized samples of a sine wave at the predetermined clock rate. The frequency setting word is applied to the adders at a reduced clock rate that is lower than the predetermined clock rate so that the adders operate at the reduced clock rate.

Abstract: A thin-film electroluminescent display panel system has a plurality of vertical column electrodes driven by column driver circuits and a plurality of horizontal row electrodes driven by row driver circuits. The system includes a row driver control circuit that enables the row drivers in a first sequence during a first display frame so that write voltage pulses are applied to the row electrodes in order from the top to the bottom of the display panel. The row driver control circuit enables the row drivers in a second sequence during a second display frame so that the write voltages are applied to the row electrodes in the reverse order from the bottom of the display panel to the top of the display panel.

Abstract: A sustainer for an AC plasma panel is disclosed, wherein two MOSFET transistors are used to alternatively, selectively provide a two level output signal which is used to maintain the emission of light from the plasma panel. The sustainer circuitry requires only a single logic input to control both transistors, and prevents both transistors from conducting simultaneously. The slew rate of the sustainer output is controlled to prevent noise generation, and circuitry is included to prevent high frequency oscillations in the transistors.

Abstract: A direction finding antenna for use in missiles and the like may include arrays of log periodic monopole antennas. The antennas may be constructed of thin, metallic stub regions laminated to an insulative support backing as a part of a wing of a missile. The antennas are triangular in shape in order to provide improved performance and to conform to the shape of wings on the missile. The antennas perform an aerodynamic function as parts of the wings as well as performing an electromagnetic function in the direction finding system. The antennas are provided with parallel feed lines which extend along the base of the triangular antenna, connecting with antenna stubs on both sides of the support backing, and connecting together at the forward end of the antenna. The antenna stubs are generally rectangular metallic sheets arranged in order of increasing length on the support backing. Electrically longer antenna stubs may be provided with zig-zag convolutions for improved performance at lower radio frequencies.

Abstract: Voltage pulser circuits are utilized to selectively, alternately supply high voltage to, or ground the high voltage input of plasma panel driver chips. High voltage is supplied to a driver chip only when the driver chip must perform an addressing pulse. The grounding operation, which is induced by shorting the high voltage input of a driver chip to the ground input of the chip, greatly reduces the amount of power which must be dissipated in the driver chip. The use of the voltage pulser circuit also allows full slew rate control of the output pulse which the driver chips supply to the plasma panel.

Abstract: A brightness control using modular waveform techniques is disclosed which enables a wide range of brightness control not affected by the order in which functions are executed. 512 cell parallel addressing is used, enabling the border electrodes to be discharged only once during each extended cycle, thus lowering the intensity of light emitted from the borders by at least a factor of 5. An erase before write technique is described which allows an erase operation to be inserted into a write function without extending the length of the write function, thus doubling the maximum data rate of the plasma panel display system.

Abstract: A signal encoder and classifier particularly adapted to speech recognition includes a buffer which is independently addressed by a new data writing address system and a buffered data reading system so that writing and reading of data may be accomplished on a time shared basis. This time shared operation permits serial writing and reading of the pattern data without interrupting income signal storage. The reading data address system utilizes stored addresses identifying the beginning and end of the signal patterns for addressing sequential patterns from the buffer.

Abstract: A simplified, speaker independent, selected vocabulary, word recognizing microcomputer functions without the use of a typical front end filtering network. The microcomputer identifies vowel-like fricative-like, and silence signal states within a word or phrase by counting speech pattern zero crossings during sequential time periods. Variable zero crossing count thresholds are used to identity states based upon previously identified states, and histeresis is provided, through the use of state time measurement, to prevent state oscillations which would result in erroneous state sequences. The microcomputer, by monitoring zero crossings, defines words as a sequence of vowel-like, fricative-like, and silence states. By limiting the recognizable vocabulary to words which have dissimilar sequences, the incoming speech pattern may be recognized by comparison with state templates defining the limited vocabulary stored in the microcomputer's memory.