Patents Assigned to Interuniversitair Microelektronica Centrum (IMEC)
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Publication number: 20130043132Abstract: A device for manipulating magnetic or magnetizable objects in a medium is provided. The device has a surface lying in a plane and comprises a set of at least two conductors electrically isolated from each other, wherein the at least two conductors are adapted for both generating a magnetophoresis force for moving the magnetic or magnetizable objects over the surface of the device in a direction substantially parallel to the plane of the surface, and generating a dielectrophoresis force for moving the magnetic or magnetizable objects in a direction substantially perpendicular to the plane of the surface. Also provided is a method for manipulating magnetic or magnetizable objects in a medium. The method uses a combined magnetophoresis and dielectrophoresis actuation principle for controlling in-plane as well as out-of-plane movement of the magnetic or magnetizable objects.Type: ApplicationFiled: August 23, 2007Publication date: February 21, 2013Applicants: Katholieke Universiteit Leuven, Interuniversitair Microelektronica Centrum (IMEC)Inventors: Chengxun Liu, Liesbet Lagae
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Publication number: 20120279837Abstract: An electrostatically actuatable micro electromechanical device is provided with enhanced reliability and lifetime. The electrostatically actuatable micro electromechanical device comprises: a substrate, a first conductor fixed to the top layer of the substrate, forming a fixed electrode, a second conductor fixed to the top layer of the substrate, and a substrate area. The second conductor is electrically isolated from the first conductor and comprises a moveable portion, suspended at a predetermined distance above the first conductor, the moveable portion forming a moveable electrode which approaches the fixed electrode upon applying an actuation voltage between the first and second conductors. The selected substrate surface area is defined as the orthogonal projection of the moveable portion on the substrate between the first and second conductors. In the substrate surface area at least one recess is provided in at least the top layer of the substrate.Type: ApplicationFiled: March 31, 2009Publication date: November 8, 2012Applicants: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Ingrid De Wolf, Xavier Rottenberg, Piotr Czarnecki, Philippe Soussan
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Publication number: 20110309457Abstract: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.Type: ApplicationFiled: June 23, 2011Publication date: December 22, 2011Applicants: Koninkiijke Philips Electronics N.V., Interuniversitair Microelektronica centrum (IMEC)Inventors: Kirklen Henson, Radu Catalin Surdeanu
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Publication number: 20110311227Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.Type: ApplicationFiled: April 4, 2008Publication date: December 22, 2011Applicants: Universiteit Gent, Interuniversitair Microelektronica Centrum (IMEC)Inventors: Peter Ossieur, Tine De Ridder, Johan Bauwelinck, Xing Zhi Qiu, Jan Vandewege
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Publication number: 20110230172Abstract: Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point.Type: ApplicationFiled: February 17, 2011Publication date: September 22, 2011Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Sofie Pollin, Bruno Bougard, Gregory Lenoir, Francky Catthoor
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Patent number: 8020163Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).Type: GrantFiled: November 24, 2004Date of Patent: September 13, 2011Assignees: Interuniversitair Microelektronica Centrum (IMEC), Xilinx, Inc.Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
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Publication number: 20110026921Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.Type: ApplicationFiled: April 4, 2008Publication date: February 3, 2011Applicants: Interuniversitair Microelektronica Centrum (IMEC), Universiteit GentInventors: Peter Ossieur, Tine De Ridder, Johan Bauwelinck, Xing Zhi Qiu, Jan Vandewege
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Publication number: 20100285656Abstract: The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapour deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained.Type: ApplicationFiled: June 16, 2006Publication date: November 11, 2010Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Santiago Cruz Esconjauregui, Caroline Whelan, Karen Maex
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Patent number: 7831951Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.Type: GrantFiled: June 11, 2007Date of Patent: November 9, 2010Assignees: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, University of PatrasInventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins
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Publication number: 20100225369Abstract: The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements.Type: ApplicationFiled: February 2, 2007Publication date: September 9, 2010Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventor: Mustafa Badaroglu
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Publication number: 20100164487Abstract: The present invention relates to a device and corresponding method for ultrafast controlling of the magnetization of a magnetic element. A device (100) includes a surface acoustic wave generating means (102), a transport layer (104), which is typically functionally and partially structurally comprised in said SAW generating means (102), and at least one ferromagnetic element (106). A surface acoustic wave is generated and propagates in a transport layer (104) which typically consists of a piezo-electric material. Thus, strain is induced in the transport layer (104) and in the ferromagnetic element (106) in contact with this transport layer (104). Due to magneto elastic coupling this generates an effective magnetic field in the ferromagnetic element (106). If the surface acoustic wave has a frequency substantially close to the ferromagnetic resonance (FMR) frequency ?FMR the ferromagnetic element (106) is absorbed well and the magnetization state of the element can be controlled with this FMR frequency.Type: ApplicationFiled: December 29, 2009Publication date: July 1, 2010Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Wouter Eyckmans, Liesbet Lagae
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Publication number: 20100127233Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.Type: ApplicationFiled: August 31, 2007Publication date: May 27, 2010Applicants: NXP, B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Ludovic Goux, Dirk Wouters
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Publication number: 20100096618Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.Type: ApplicationFiled: December 19, 2007Publication date: April 22, 2010Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Francesca Iacopi, Philippe M. Vereecken
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Publication number: 20100090192Abstract: For improved scalability of resistive switching memories, a cross-point resistive switching structure is disclosed wherein the plug itself is used to store the resistive switching material and where the top electrode layer is self-aligned to the plug using, for example, chemical-mechanical-polishing (CMP) or simply mechanical-polishing.Type: ApplicationFiled: August 31, 2007Publication date: April 15, 2010Applicants: NXP, B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Ludovic Goux, Dirk Wouters
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Publication number: 20100090251Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.Type: ApplicationFiled: November 20, 2007Publication date: April 15, 2010Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&DInventors: Anne Lorenz, Joff Derluyn, Joachim John
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Patent number: 7671768Abstract: The invention relates to an N-bit digital-to-analogue converter (DAC) system, comprising—a DAC unit comprising an N-bit master DAC and a slave DAC, yielding a master DAC unit output signal and a slave DAC unit output signal, respectively, said N-bit master DAC having an output step size,—an adder unit combining the master DAC unit output signal and the slave DAC unit output signal, and—a means for storing correction values for at least the master DAC, said correction values being used by the slave DAC, whereby the DAC system is arranged for master DAC output corrections with a size in absolute value higher than half of the output step size.Type: GrantFiled: May 2, 2005Date of Patent: March 2, 2010Assignees: Interuniversitair Microelektronica Centrum (IMEC), Universiteit HasseltInventor: Ward De Ceuninck
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Publication number: 20100032812Abstract: A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of the depositing and/or annealing steps are selected such that a predetermined average stress and a predetermined strain gradient are obtained in the predetermined part of the silicon germanium layer. Preferably a plasma assisted deposition technique is used for depositing the silicon germanium layer, and a pulsed excimer laser is used for local annealing, with a limited thermal penetration depth. Structural silicon germanium layers for surface micromachined structures can be formed at temperatures substantially below 400° C., which offers the possibility of post-processing micromachined structures on top of a substrate comprising electronic circuitry such as CMOS circuitry.Type: ApplicationFiled: December 21, 2006Publication date: February 11, 2010Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), AMERICAN UNIVERSITY CAIROInventors: Sherif Sedky, Ann Witvrouw
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Patent number: 7649722Abstract: A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.Type: GrantFiled: September 14, 2006Date of Patent: January 19, 2010Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Steven Thijs, Natarajan Mahadeva Iyer, Dimitri Linten
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Patent number: 7646138Abstract: A thickness shear mode (TSM) resonator is described, comprising a diamond layer. The diamond layer is preferably a high quality diamond layer with at least 90% sp3 bonding or diamond bonding. A method for manufacturing such a resonator is also described. The thickness shear mode resonator according to embodiments described herein may advantageously be used in biosensor application and in electrochemistry applications.Type: GrantFiled: November 21, 2007Date of Patent: January 12, 2010Assignees: Interuniversitair Microelektronica Centrum (IMEC), Universiteit HasseltInventor: Oliver Williams
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Patent number: 7643709Abstract: A slanted grating coupler for coupling a radiation beam between a waveguide lying substantially in a plane on a substrate and an optical element outside that plane is provided, whereby the slanted grating coupler has a good coupling efficiency for medium or low index contrast material systems. Furthermore, a method for manufacturing the slanted grating coupler is provided. The slanted grating coupler comprises a plurality of slanted slots extending through the waveguide core and being arranged successively in the propagation direction of the waveguide. In at least part of the coupling region, the size of the slanted slots in a lateral direction, being a direction within the waveguide plane and perpendicular to the propagation direction of the waveguide, is smaller than the lateral size of the waveguide core. Successive slots are displaced with respect to each other in the lateral direction.Type: GrantFiled: May 8, 2007Date of Patent: January 5, 2010Assignees: Interuniversitair Microelektronica Centrum (IMEC), Universiteit GentInventors: Frederik Van Laere, Roeland Baets, Dries Van Thourhout, Dirk Taillaert