Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate and made of a high-dielectric-constant material composed of a plurality of layers stacked perpendicularly to a principal surface of the semiconductor substrate and associated with respective phases; and a gate electrode formed on the gate insulating film.

Abstract: A method for removing organic contaminants from a semiconductor surface whereby the semiconductor is held in a tank and the tank is filled with a fluid such as a liquid or a gas. Organic contaminants, such as photoresist, photoresidue, and dry etched residue, occur in process steps of semiconductor fabrication and at times, require removal. The organic contaminants are removed from the semiconductor surface by holding the semiconductor inside a tank. The method may be practiced using gas phase processing or liquid phase processing. The tank is filled with a gas mixture, a liquid, and/or a fluid, such as water, water vapor, ozone and/or an additive acting as a scavenger (a substance which counteracts the unwanted effects of other constituents of the system).

Abstract: Test circuitry and test methods performing supply current measurement is presented. The test circuitry can be but is not limited to be on-chip. The supply current, also denoted test current, can be transient. The test circuitry and methods do not cause additional power supply voltage degradation. The test circuitry and methods provide detection capabilities for open defects, causing significant reduction of the transient supply current.

Abstract: A method and apparatus for dispensing a liquid on the surface of a localized zone of a substrate, for example for cleaning of etching purposes. Along with the liquid, a gaseous tensio-active substance is supplied, which is miscible with said liquid and when mixed with the liquid, reduces the surface tension of said liquid, thus containing the liquid in a local zone of the substrate surface.

Abstract: A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase. The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.

Abstract: The present invention is related to a system for transferring a beam of electromagnetic radiation having a vacuum wavelength. The system according to the invention includes a first dielectric medium, a second dielectric medium and a dielectric layer in between the first and the second medium. The dielectric layer has a periodicity of the dielectric properties parallel to the layer. The periodicity has a period that is smaller than the wavelength of the electromagnetic radiation in the second dielectric medium.

Abstract: The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: A system for evaluating the thermal impedance of packaged semiconductor chips. The measuring apparatus includes a thermostatic bath filled with a dielectric liquid and a temperature sensor for measuring the temperature of the bath. The semiconductor chip is subjected to a calibration step followed by a thermal response measurement step. Increasing the power pulse length allows measurement of the steady-state junction-to-case thermal resistance. The measuring apparatus and method is further used for tracing in-situ degradation of packaged semiconductor chips due to power cycling.

Abstract: A differential pair of optoelectronic pnpn devices provided with probing impedances allows such pair to operate as an optical to optical, optical to electrical and electrical to optical transceiver. This basic transceiver is useful in situations where information transport is needed between two or more locations, e.g., optical interconnects in electronic computing systems. The transceiver can be repeated in arrays in connection with Si-VLSI circuitry for high bandwidth optical interconnect applications.

Abstract: In an optical projection system for use in projection printing of masks to wafers, comprising an illumination system including a light source and a mask positioned in the optical path of the illumination system, an optical phase structure is positioned in the optical path between the light source and the mask. The phase structure comprises a pattern of distributed transparent features having at least one refractive index, the transparent features of said phase structure being related in position and orientation to the opaque features of the mask.

Abstract: A device for detecting infrared radiation which comprises a sensitive arm which, over at least a portion of its length, consists of bimetal. One end of said arm is joined to a membrane.

Abstract: An integrated tunable optical filter comprising a substrate made of a semiconducting material. The substrate includes first and second sections. The first section forms a tunable transmission filter, based on a codirectional coupler having a low selectivity. The second section forms a reflection filter with a reflection spectrum containing a number of peaks. A first injector, designed for current injection into said first section, is provided. Thus, the filter response of the first section is shifted in wavelength over a large wavelength range. There is also a second injector, designed for current injection into the second section. As a result, the reflective spectrum of the second section is slightly shifted in wavelength, in such a way that one reflection peak of the reflection spectrum corresponds to the coupling wavelength of the first section. Consequently, the total filter response has a very narrow bandwidth and wide tunability.

Abstract: A method for measuring the resistance or conductivity between two or more conductors which are placed against a semiconductor element, the conductors are placed either in contact with the top surface or one conductor is placed in contact with the top surface and the other conductor is in the form of a large ohmic contact applied to the bottom surface of the semiconductor element. In order to bring the contact resistance between the top conductor(s) and the element to, and hold it at, a predetermined value during measuring, the conductor(s) are held at a constant distance and/or under constant pressure relative to the semiconductor element by use of a scanning proximity microscope. The top conductor may have a boron implanted diamond tip. The carrier profile of the semiconductor element is determined from previously derived calibration curves.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: The system comprises a latent image detection device comprising an alignment device which uses non-actinic radiation (10) and which is intended for aligning the mask pattern with respect to the substrate (3) and is designed for detecting the measure of coincidence of a mask alignment feature and a substrate alignment feature (8). The alignment device is provided with a radiation-sensitive detection system (6) which is connected to an electronic signal circuit in which the amplitude of the radiation incident on the detection system is determined, which originates from a latent image, formed in the photosensitive layer, of a mask feature, in which a spatial frequency occurs which is approximately equal to the useful resolving power of the projection lens system and considerably greater than the resolving power of the alignment device.

Abstract: An integrated tunable optical filter comprising a substrate made of a semiconducting material. The substrate includes first and second sections. The first section forms a tunable transmission filter, based on a codirectional coupler having a low selectivity. The second section forms a reflection filter with a reflection spectrum containing a number of peaks. A first injector, designed for current injection into said first section, is provided. Thus, the filter response of the first section is shifted in wavelength over a large wavelength range. There is also a second injector, designed for current injection into the second section. As a result, the reflective spectrum of the second section is slightly shifted in wavelength, in such a way that one reflection peak of the reflection spectrum corresponds to the coupling wavelength of the first section. Consequently, the total filter response has a very narrow bandwidth and wide tunability.