Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.

Abstract: The present invention relates to processes for fabrication of Vertical MISFET devices or a stack of several of such devices. The Vertical MISFET device comprises a highly doped drain region, a non or lowly doped channel region and a source region forming a heterojunction with the channel region. The source region comprises a lowly doped part which contacts the channel region and a highly doped part which contacts the lowly doped part.

Abstract: The present invention relates to methods for fabricating Fully Overlapped Nitride-Etch Defined (Fond) devices. These methods permit the lateral dimension and depth of the lowly-doped source and drain extensions to be independently controlled and well defined.