Abstract: A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light.

Abstract: A correlated double sampled (CDS) pixel is provided. The CDS pixel comprises an image sensing device, an inverting amplifier, a capacitor, and first and second switches. The image sensing device generates charge based on image content. The inverting amplifier is in operable communication with the image sensing device. The capacitor is configured as a feedback to the inverting amplifier, wherein the first capacitor configured as a switching capacitor and configured to integrate an image signal received by the image sensing device. The first switch is in operable communication with the inverting amplifier and is configured to control sample timing of a correlated offset signal. The second switch is in operable communication with the image sensing device and is configured to control sample timing of the image signal.

Abstract: A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: An image comprising a plurality of pixels at a predetermined pixel pitch, is received, A plurality of image intensity signals, are received at readout circuitry responsive to an image intensity per pixel. A portion of the received image is divided into a plurality of fixed paxels, each paxel comprising a rectilinear collection of pixels, having a first length and first predetermined number of rows, and second width having second predetermined number of columns. The plurality of fixed paxels are provided to a respective plurality of configurable Analog to Digital Converters (ADCs) responsive to a respective plurality of paxels and configurable to generate respective ADC output signals that implement a tradeoff between Effective Number of Bits (ENoB) and power consumption while maintaining a substantially fixed spatial frequency. Some paxels corresponding to a first predetermined fixation point are digitized with higher ENoB than the other paxels. A foveated image is generated.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: An image comprising a plurality of pixels at a predetermined pixel pitch, is received, A plurality of image intensity signals, are received at readout circuitry responsive to an image intensity per pixel. A portion of the received image is divided into a plurality of fixed paxels, each paxel comprising a rectilinear collection of pixels, having a first length and first predetermined number of rows, and second width having second predetermined number of columns. The plurality of fixed paxels are provided to a respective plurality of configurable Analog to Digital Converters (ADCs) responsive to a respective plurality of paxels and configurable to generate respective ADC output signals that implement a tradeoff between Effective Number of Bits (ENoB) and power consumption while maintaining a substantially fixed spatial frequency. Some paxels corresponding to a first predetermined fixation point are digitized with higher ENoB than the other paxels. A foveated image is generated.

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a sigma-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: An amplifier capable of driving an analog load is provided. The amplifier can be constructed and arranged to operate as at least one circuit selected from the group consisting of a class D amplifier, voltage regulator, audio amplifier, servo amplifier, servo control, digital control, switching power supply, and switching power amplifier. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon an input signal (e.g., an analog input signal) to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses.

Abstract: An amplifier capable of driving an analog load is provided. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon a digital input signal to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses. The output stage is coupled to the pulse processing circuit and has first state wherein the output stage provides analog noise-shaped output energy pulses to a load and a second state where the output energy delivered is essentially zero. The feedback loop is coupled between the output stage and the SDM.

Abstract: A sigma delta modulator (SDM) data converter system is provided. The SDM data converter system comprises a signal path, a feedback signal path, and a multi-bit quantizer disposed in a feedforward path. The signal path receives an input signal to be processed. The feedback signal path provides a feedback signal that is subtracted from the input signal. The multi-bit quantizer is disposed in the feedforward path so as to receive the input signal after the feedback signal has been subtracted from it. Te multi-bit quantizer uses feedforward dynamic element matching (DEM) to spectrally shape mismatch errors in the SDM data conversion system and produce an output signal, wherein the output signal of the multi-bit quantizer is used for at least a portion of the feedback signal.

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).