Abstract: A synchronizing high-speed clock divider has a Clk input, a Clks input, and a reset input configured to correct phase misalignment on clock divider outputs caused by phase skew between a Clk input signal and a Clks input signal, and comprises a reset synchronizer configured to generate at least one synchronous internal reset signal in response to a reset signal and the Clk input signal, a first clock divider configured to receive the Clk input signal on the Clk input and a reset signal on a first clock divider reset input to provide a Clk out signal, a second clock divider configured to receive the Clks input signal on the Clks input and the reset signal on a second clock divider reset input to provide a Clks out signal, a phase skew detector configured to detect a phase alignment between the Clk out signal and the Clks out signal, and a phase skew corrector coupled to the phase skew detector and the second clock divider configured to change the phase alignment to be within a same phase as the first clock div

Abstract: A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.

Abstract: A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.

Abstract: Temperature sensors for integrated circuits that use back-gate bias for low power operation. A temperature sensor can comprise a voltage-gate-source generator having sensing transistors; an Ibias generator; a back-gate bias generator; and a temperature read-out circuit. In a calibration mode, the temperature sensor determines a back-gate bias voltage and a resistor trimming code to be used during functional operation.

Abstract: A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.

Abstract: A bandgap reference voltage generator, comprises: a bias circuit configured to generate a start signal; a startup circuit having at least two serially-connected transistors configured to receive the start signal; a proportional-to-absolute-temperature (“PTAT”) generation circuit having a first current mirror, an amplifier, a resistor, and transistors; and a complementary-to-absolute-temperature (“CTAT”) generation circuit having a second current mirror, a passive network of resistors, and at least one transistor. The at least two serially-connected transistors are connected across a first input of the amplifier and a second input of the amplifier. An output of the amplifier is coupled to the first current mirror and the second current mirror. The passive network of resistors is coupled across outputs of the second current mirror. The CTAT generation circuit has an output node for outputting a bandgap reference voltage.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.

Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.

Abstract: An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: A duty cycle detection circuit, comprises a charge storage component and compare logic. The charge storage component has at least one capacitor, at least one switch, and, at least one current source. A clock signal is used to operate the at least one switch for charging the at least one capacitor using the at least one current source. The charge storage component outputs a first signal indicative of an amount of charge stored when the clock signal is logic high and a second signal indicative of an amount of charge stored when the clock signal is logic low. The compare logic compares the first signal and the second signal to determine a duty cycle for the clock signal.

Abstract: A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage.

Abstract: A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.

Abstract: A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.

Abstract: A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.