Patents Assigned to INVENSAS BONDING TECHNOLOGIES, INC.
  • Patent number: 11476213
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 18, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • Patent number: 11462419
    Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 4, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Belgacem Haba
  • Patent number: 11417576
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11393779
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 19, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Belgacem Haba, Rajesh Katkar
  • Patent number: 11385278
    Abstract: A bonded structure is disclosed. The bonded structure can include a first semiconductor element having a first front side and a first back side opposite the first front side. The bonded structure can include a second semiconductor element having a second front side and a second back side opposite the second front side, the first front side of the first semiconductor element directly bonded to the second front side of the second semiconductor element along a bond interface without an adhesive. The bonded structure can include security circuitry extending across the bond interface, the security circuitry electrically connected to the first and second semiconductor elements.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Guy Regev
  • Patent number: 11380597
    Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Rajesh Katkar, Liang Wang
  • Patent number: 11373963
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Patent number: 11367652
    Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 21, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 11355404
    Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 7, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
  • Patent number: 11348801
    Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 31, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Guilian Gao
  • Publication number: 20220165692
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Application
    Filed: December 22, 2021
    Publication date: May 26, 2022
    Applicant: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Rajesh Katkar, Guilian GAO, Laura Wills MIRKARIMI
  • Patent number: 11296053
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11296044
    Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Javier A. Delacruz, Shaowu Huang, Liang Wang, Gaius Gillman Fountain, Jr., Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 11289372
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 29, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 11276676
    Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 15, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Paul M. Enquist, Belgacem Haba
  • Patent number: 11264345
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 1, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Paul M. Enquist
  • Patent number: 11257727
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 22, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11256004
    Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 22, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed
  • Patent number: 11244916
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 8, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Patent number: 11244920
    Abstract: Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 8, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Cyprian Emeka Uzoh