Abstract: An integrated circuit chip that receives data on an asynchronous communications bus from an external device and receives data from asynchronous internal device is capable of switching from synchronous operation to asynchronous operation without any loss of data. The chip does not switch off the system clock while there is activity on the communications bus. Additionally, the communications bus has a minimum event time greater than the time fo one and a half cycles of the system clock plus enough timing margin for an asynchronous update to occur.