Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Abstract: The present invention provides in-situ positioning of a sensor within each functional block, as well as at critical locations, of a semiconductor system. Sensor quantity and location is optimized for maximum sensitivity to known process variations. The sensor models a behavior of the location in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. Based on the output, one or more functional blocks are modified to reduce semiconductor system gradation in real-time.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Abstract: Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.