Patents Assigned to IPOWER SEMICONDUCTOR
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Patent number: 11640992Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11640994Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11640993Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11581432Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.Type: GrantFiled: July 5, 2021Date of Patent: February 14, 2023Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Patent number: 11538911Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.Type: GrantFiled: June 4, 2020Date of Patent: December 27, 2022Assignee: iPower SemiconductorInventor: Hamza Yilmaz
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Patent number: 11469313Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.Type: GrantFiled: January 19, 2021Date of Patent: October 11, 2022Assignee: IPOWER SEMICONDUCTORInventors: Hamza Yilmaz, Jong Oh Kim
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Publication number: 20220131000Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Publication number: 20220131001Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Publication number: 20220130999Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Patent number: 11251297Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: October 8, 2019Date of Patent: February 15, 2022Assignees: Ipower Semiconductor, Taiwan Semiconductor Co., Ltd.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11239352Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.Type: GrantFiled: February 28, 2020Date of Patent: February 1, 2022Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Patent number: 11233141Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.Type: GrantFiled: January 16, 2019Date of Patent: January 25, 2022Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Publication number: 20220013627Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.Type: ApplicationFiled: July 20, 2021Publication date: January 13, 2022Applicant: IPOWER SEMICONDUCTORInventor: HAMZA YILMAZ
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Publication number: 20210336051Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.Type: ApplicationFiled: July 5, 2021Publication date: October 28, 2021Applicant: IPOWER SEMICONDUCTORInventor: HAMZA YILMAZ
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Publication number: 20210226041Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.Type: ApplicationFiled: January 19, 2021Publication date: July 22, 2021Applicant: IPOWER SEMICONDUCTORInventors: HAMZA YILMAZ, JONG OH KIM
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Patent number: 11069770Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.Type: GrantFiled: June 24, 2019Date of Patent: July 20, 2021Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Patent number: 11056585Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.Type: GrantFiled: April 22, 2019Date of Patent: July 6, 2021Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Patent number: 10998438Abstract: A MOSFET device structure is formed on a semiconductor wafer. The structure includes an array of plurality of MOS gate trenches and self-aligned p+ contact trenches that are formed in a p body region. Trench depth of MOS gate trenches are deeper than the self-aligned p+ contact trenches. P doped shield regions are formed under each MOS gate trench.Type: GrantFiled: March 1, 2019Date of Patent: May 4, 2021Assignee: IPOWER SEMICONDUCTORInventor: Hamza Yilmaz
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Publication number: 20210057557Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.Type: ApplicationFiled: November 8, 2020Publication date: February 25, 2021Applicant: IPOWER SEMICONDUCTORInventor: HAMZA YILMAZ
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Publication number: 20210057556Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.Type: ApplicationFiled: November 7, 2020Publication date: February 25, 2021Applicant: IPOWER SEMICONDUCTORInventor: HAMZA YILMAZ