Abstract: Described herein are a method and apparatus for a selective SYSREF (SYStem REFerence signal) scheme that is driven by an external SYSREF source for a system that may include, for example, analog blocks, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), radio frequency (RF) arrays, as well as digital blocks, which may include JESD serializer/deserializer (SERDES) Transport and Link Layer circuitry, all of which can be operating at different clock frequencies. In one aspect, synchronization of the components is achieved when an internal SYSREF for the analog blocks is keyed off the external SYSREF, but the internal SYSREF pulse used by the digital blocks is programmatically keyed off one of the periodic internal SYSREF pulses. Additionally, a mechanism is provided for synchronization of the programmatically selected internal SYSREF across different clock domains in the digital blocks.

Abstract: A transformer based voltage controlled oscillator (VCO) is provided with a primary resonant circuit having a first inductor connected in parallel with a variable first capacitance circuit. A secondary resonant circuit is formed from a second inductor connected in parallel with a variable second capacitance circuit, and also includes a mode control circuit. The mode control circuit controls the direction of current flow through the secondary resonant circuit inductor. The first and second inductors are inductively mutually coupled in either an even mode or an odd mode in response to the mode control circuit. The VCO supplies a first resonant frequency in response to even mode operation, or a second resonant frequency, greater than the first resonant frequency, responsive to odd mode operation. The VCO may include a first electrically tunable varactor shunted across the first capacitance circuit and a second electrically tunable varactor shunted across the second capacitance circuit.

Abstract: Processing a signal by receiving an analog input signal located outside of a first Nyquist zone that is between 0 and fs/2; passing the analog input signal through an M-channel time-interleaved analog-to-digital converter (TI-ADC) to generate a TI-ADC output signal; and estimating and correcting a timing skew error in the TI-ADC output signal. Alternatively, an electronic circuit that includes an input for an analog input signal, an M-channel time-interleaved analog-to-digital converter (TI-ADC) and a timing skew error estimating and correcting circuitry. The analog input signal is located outside of a first Nyquist zone that is between 0 and fs/2. The TI-ADC receives the analog input signal and generates a TI-ADC output signal. The timing skew error estimating and correcting circuitry estimates and corrects a timing skew error in the TI-ADC output signal.

Abstract: Processing a signal by receiving an analog input signal located outside of a first Nyquist zone that is between 0 and fs/2; passing the analog input signal through an M-channel time-interleaved analog-to-digital converter (TI-ADC) to generate a TI-ADC output signal; and estimating and correcting a timing skew error in the TI-ADC output signal. Alternatively, an electronic circuit that includes an input for an analog input signal, an M-channel time-interleaved analog-to-digital converter (TI-ADC) and a timing skew error estimating and correcting circuitry. The analog input signal is located outside of a first Nyquist zone that is between 0 and fs/2. The TI-ADC receives the analog input signal and generates a TI-ADC output signal. The timing skew error estimating and correcting circuitry estimates and corrects a timing skew error in the TI-ADC output signal.